VHDL Issue Number:      0075
Classification:         Language Definition Problem
Language Version:       VHDL-87
Summary:                Ambiguity as to when parameter subtype indications are
                        elaborated.
Related Issues:         
Relevant LRM Sections:  12.3.1.1, 12.5
Key Words and Phrases:  Elaboration, subtype indication, parameter
Current Status:         Submitted
1076-1993 Disposition:  Superseded (ISAC Issues Outstanding)
Disposition Rationale:  ??
Superseded By:          1002
-----------------------
Date Submitted:         1989/02/10
Author of Submission:   Doug Dunlop
Author's Affiliation:   Intermetrics, Inc.
Author's Post Address:  4733 Bethesda Ave #415
                        Bethesda, MD  20814
Author's Phone Number:  (301) 657-3775
Author's Fax Number:    
Author's Net Address:   dunlop@inmet.inmet.com
-----------------------
Date Analyzed:          TBD
Author of Analysis:     TBD
Revision Number:        $Revision: 1.9 $
Date Last Revised:      $Date: 1995/05/13 21:53:48 $


Description of Problem
----------------------
LRM 12.3.1.1 implies that subtype indications for
parameters are elaborated when the declarative part containing the subprogram
declaration is elaborated.  LRM 12.5 (Item 2) implies that subtype indications
for parameters are elaborated when the subprogram is called.


Proposed Resolution
-------------------
This matter is related to that in IR 0066 in which Item 2 of
LRM 12.5 was put in doubt.  Following LRM 12.3.1.1 represents a negligible loss
of flexibility for the user.  Hence with regard to when subtype indications of
parameters are elaborated, we follow LRM 12.3.1.1.


VASG-ISAC Analysis & Rationale
------------------------------
TBD


VASG-ISAC Recommendation for IEEE Std 1076-1987
-----------------------------------------------
TBD


VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
TBD