VHDL Issue Number:      0084
Classification:         Language Definition Problem
Language Version:       VHDL-87
Summary:                Unclear what errors can arise during creation of
                        drivers for process.
Related Issues:         
Relevant LRM Sections:  9.2.1, 12.4.4
Key Words and Phrases:  Driver, process, elaboration
Current Status:         ISAC-Approved
1076-1993 Disposition:  Closed (All Issues Completely Addressed)
Disposition Rationale:  No language changed required
Superseded By:          N/A
-----------------------
Date Submitted:         1989/02/10
Author of Submission:   Doug Dunlop
Author's Affiliation:   Intermetrics, Inc.
Author's Post Address:  4733 Bethesda Ave #415
                        Bethesda, MD  20814
Author's Phone Number:  (301) 657-3775
Author's Fax Number:    
Author's Net Address:   dunlop@inmet.inmet.com
-----------------------
Date Analyzed:          1990/12/12
Author of Analysis:     Clive R. Charlwood
Revision Number:        $Revision: 1.9 $
Date Last Revised:      $Date: 1995/05/13 19:34:42 $


Description of Problem
----------------------
Consider the following VHDL:

          ENTITY E IS
             GENERIC(I : INTEGER);
          END E;
          ------
          ARCHITECTURE A OF WORK.E IS
             SIGNAL S : STRING(1 TO 10);
          BEGIN
             PROCESS
             BEGIN
                IF I >= 1 AND I <= 10 THEN
                   S(I) <= '0';
                END IF;
             END PROCESS;
          END A;

If architecture A in the above is elaborated and the value 0 is passed for I,
what happens during the creation of the drivers for the process?


Proposed Resolution
-------------------
This is not an error situation.  The simulator may issue an
elaboration-time warning.  This is true regardless of the logic that surrounds
the signal assignment.  E.g., had the process above been written

             PROCESS
             BEGIN
                S(I) <= '0';
             END PROCESS;

there would still be no elaboration-time error if the architecture was
elaborated with the value 0 passed for I (although an execution-time error
would occur subsequently).


VASG-ISAC Analysis & Rationale
------------------------------
The proposed resolution is rejected. This is an "elaboration time" error.

The first sentence of the first paragraph of LRM 9.2.1 states that 

        "Every signal assignment statement in a process statement 
         defines a set of drivers for certain scalar signals. ..."

This means that every signal assignment statement has at least
one driver associated with it (regardless of whether the statement
can/will ever be executed). Therefore, in the first example above 
a driver will always be created for S. If the generic is passed
a value of 0 then an error must be issued when the driver is created
(i.e.,  at elaboration time).

This does not burden/restrict a designer. Since, the model could
more naturally be written using an IF generate statement.


VASG-ISAC Recommendation for IEEE Std 1076-1987
-----------------------------------------------
No change in the interpretation of the 1076-1987 LRM is required.


VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
No changes to future LRMs are required.