VHDL Issue Number: 0085 Classification: Language Definition Problem Language Version: VHDL-87 Summary: Subelement of a local as an actual in a binding indication is unclear. Related Issues: Relevant LRM Sections: 5.3.1.2 Key Words and Phrases: Binding indication, subelement association Current Status: Submitted 1076-1993 Disposition: Closed (All Issues Completely Addressed) Disposition Rationale: LRM is clear now, Section 5.2.1.2 addresses this. Superseded By: N/A ----------------------- Date Submitted: 1989/02/10 Author of Submission: Doug Dunlop Author's Affiliation: Intermetrics, Inc. Author's Post Address: 4733 Bethesda Ave #415 Bethesda, MD 20814 Author's Phone Number: (301) 657-3775 Author's Fax Number: Author's Net Address: dunlop@inmet.inmet.com ----------------------- Date Analyzed: TBD Author of Analysis: TBD Revision Number: $Revision: 1.9 $ Date Last Revised: $Date: 1995/05/13 19:34:42 $ Description of Problem ---------------------- LRM 5.3.1.2 states that "each local ... must be associated as an actual with at least one formal". It is unclear if this requirement is met if one subelement (but not the other subelements) of the local is associated with a formal or whether each subelement of the local must be associated with a formal. Proposed Resolution ------------------- It seems to make most sense to require that each subelement of the local be associated with a formal. This will be, in general, an elaboration- time check. VASG-ISAC Analysis & Rationale ------------------------------ TBD VASG-ISAC Recommendation for IEEE Std 1076-1987 ----------------------------------------------- TBD VASG-ISAC Recommendation for Future Revisions --------------------------------------------- TBD