VHDL Issue Number:      0086
Classification:         Language Definition Problem
Language Version:       VHDL-87
Summary:                The meaning of the direction in an index
                        specification is unclear.
Related Issues:         0050
Relevant LRM Sections:  1.3.1
Key Words and Phrases:  Generate statement, index specification
Current Status:         ISAC-Approved
1076-1993 Disposition:  Closed (All Issues Completely Addressed)
Disposition Rationale:  LRM was updated.
Superseded By:          N/A
-----------------------
Date Submitted:         1989/02/10
Author of Submission:   Doug Dunlop
Author's Affiliation:   Intermetrics, Inc.
Author's Post Address:  4733 Bethesda Ave #415
                        Bethesda, MD  20814
Author's Phone Number:  (301) 657-3775
Author's Fax Number:    
Author's Net Address:   dunlop@inmet.inmet.com
-----------------------
Date Analyzed:          1991/03/21
Author of Analysis:     Alex Zamfirescu
Revision Number:        $Revision: 1.9 $
Date Last Revised:      $Date: 1995/08/03 17:59:09 $


Description of Problem
----------------------
Let L be a label on a generate loop.  Is the block
configuration

              for L(1 to 10) ... end for;

equivalent to

              for L(10 downto 1) ... end for;

or does the direction of the discrete range affect the implicit block
statements to which the block configuration is applicable?  If this discrete
range were treated as in a choice of an aggregate (I0050), its
direction would have no significance; if the discrete range were treated as
a slice name, its direction (with respect to the direction of the prefix)
would be significant.  Presumably, in the latter case, the
direction of the discrete range in an index specification would have meaning
with respect to the direction of the discrete range in the corresponding
generate loop.


Proposed Resolution
-------------------
It seems to make most sense to treat index specification discrete
ranges like those appearing as choices in aggregates.  Hence their directions
have no particular meaning.  Specifically, the implicit block statements that
are applicable for a block configuration with a discrete range index
specification are those whose generate parameter values are greater than or
equal to the lower bound of the discrete range and less than or equal to the
upper bound of the discrete range (see LRM 3.1).


VASG-ISAC Analysis & Rationale
------------------------------
Since, (a) the binding indication of the configuration specification binds each
component instance to the same design entity, (b) index information, if used to
identify connections that are to be made for each generated component, is used
only in the port or generic maps, and (c) for the case of the generated
components binded to the same design entity, the order of elaboration is
transparent to the user, we concluded that, the direction of the discrete
range in a block configuration will not affect the implicit block statements.

No meaningful interpretation was found for the case when direction of the
discrete range in an index specification would have meaning with respect to
the direction of the discrete range in the corresponding generate loop.


VASG-ISAC Recommendation for IEEE Std 1076-1987
-----------------------------------------------
The intent of the language is to allow any direction of a discrete
range that appears in an index specification for a block configuration.
The direction of a discrete range is used in an index specification
(as in an aggregate, see IR0050) just to express a correct discrete range,
and it has no other significance.


VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
If a set concept is introduced into the language that should be used
to flag that direction of the discrete range is irrelevant in this case.