VHDL Issue Number:      0087
Classification:         Language Definition Problem
Language Version:       VHDL-87
Summary:                Unclear context of evaluation for formal part of
                        block map aspects.
Related Issues:         
Relevant LRM Sections:  9.1
Key Words and Phrases:  block statement, block map aspect, block formals
Current Status:         Submitted
1076-1993 Disposition:  Superseded (ISAC Issues Outstanding)
Disposition Rationale:  
Superseded By:          1009
-----------------------
Date Submitted:         1989/02/10
Author of Submission:   Doug Dunlop
Author's Affiliation:   Intermetrics, Inc.
Author's Post Address:  4733 Bethesda Ave #415
                        Bethesda, MD  20814
Author's Phone Number:  (301) 657-3775
Author's Fax Number:    
Author's Net Address:   dunlop@inmet.inmet.com
-----------------------
Date Analyzed:          TBD
Author of Analysis:     TBD
Revision Number:        $Revision: 1.10 $
Date Last Revised:      $Date: 1995/05/13 19:34:42 $


Description of Problem
----------------------
The actuals in an association element in a block port
map or generic map aspect are evaluated in the context of the enclosing
declarative region (LRM 9.1).  The obvious intent is to make block
map associations parallel other forms of association in the language in that
formals are not directly visible in the map aspect and instead are visible by
selection at certain specific places in the map aspect.  To achieve this
effect, the index expressions (if any) in the names of the formals should
also be evaluated in the enclosing declarative region.


Proposed Resolution
-------------------
The above evaluation of index expressions in the formal name is
assumed.


VASG-ISAC Analysis & Rationale
------------------------------
TBD


VASG-ISAC Recommendation for IEEE Std 1076-1987
-----------------------------------------------
TBD


VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
TBD