VHDL Issue Number:      0088
Classification:         Language Definition Problem
Language Version:       VHDL-87
Summary:                Overloaded convertible operands make type analysis
                        very difficult.
Related Issues:         
Relevant LRM Sections:  7.3.5, 7.2.4
Key Words and Phrases:  Convertible operand, universal type, physical division
Current Status:         Submitted
1076-1993 Disposition:  Superseded (ISAC Issues Outstanding)
Disposition Rationale:  N/A
Superseded By:          1010
-----------------------
Date Submitted:         1989/02/10
Author of Submission:   Doug Dunlop
Author's Affiliation:   Intermetrics, Inc.
Author's Post Address:  4733 Bethesda Ave #415
                        Bethesda, MD  20814
Author's Phone Number:  (301) 657-3775
Author's Fax Number:    
Author's Net Address:   dunlop@inmet.inmet.com
-----------------------
Date Analyzed:          TBD
Author of Analysis:     TBD
Revision Number:        $Revision: 1.9 $
Date Last Revised:      $Date: 1995/05/13 21:53:48 $


Description of Problem
----------------------
Both Ada and VHDL define a "convertible universal
operand".  In both languages, these are the operands for which implicit
conversion from a universal type to a non-universal type is allowed.  In Ada,
a convertible operand always has single meaning and this fact has a simplifying
effect on the type-analysis process for Ada expressions.  Unlike Ada, VHDL
defines division with operands of some physical type to be a convertible
universal operand.  Thus if one meaning of an expression is division with
operands of some physical type and another meaning is division with operands
of a non-physical type, the expression itself may or may not be a convertible
operand.  To illustrate this problem, consider the following VHDL declarations:

type int1 is ...; -- integer type
type int2 is ...; -- integer type
type int3 is ...; -- integer type
type phy  is ...; -- physical type

function f return int1;  -- f1
function f return phy;   -- f2
function g return int2;  -- g1
function g return phy;   -- g2
function h return int2;  -- h1
function h return phy;   -- h2
function j return int3;  -- j1
function j return phy;   -- j1
function k return int1;  -- k1
function k return int2;  -- k2

The problem is apparent in detecting INTEGER (f/f + g/g + h/h + k) as illegal
while at the same time allowing INTEGER (j/j + g/g + h/h + k) as valid VHDL.

In Ada, because a convertible universal operand cannot have multiple meanings,
a common implementation strategy is to count the number of implicit
conversions required for each meaning of an expression.  Where there are
multiple meanings of the expression with the same result type, the meaning
requiring the fewest number of implicit conversions is selected.  The other
meanings of the type must be discarded because their additional implicit
conversions were not necessary and therefore should not have been performed.
It is the existence of overloaded convertible universal operands that makes
this technique of implementing implicit conversions not correct for VHDL.


Proposed Resolution
-------------------
This problem will be taken up with the VHDL language maintenance
group.  For the time being a division operation with more than one meaning
will not be considered a convertible universal operand.


VASG-ISAC Analysis & Rationale
------------------------------
TBD


VASG-ISAC Recommendation for IEEE Std 1076-1987
-----------------------------------------------
TBD


VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
TBD