VHDL Issue Number:      0089
Classification:         Language Definition Problem
Language Version:       VHDL-87
Summary:                Reference to a formal from within its own interface
                        list is unclear.
Related Issues:         
Relevant LRM Sections:  4.3.3.1, 12.2.2, 12.5
Key Words and Phrases:  Elaboration, interface object
Current Status:         Analyzed
1076-1993 Disposition:  Closed (All Issues Completely Addressed)
Disposition Rationale:  LRM was updated.
Superseded By:          N/A
-----------------------
Date Submitted:         1989/02/10
Author of Submission:   Doug Dunlop
Author's Affiliation:   Intermetrics, Inc.
Author's Post Address:  4733 Bethesda Ave #415
                        Bethesda, MD  20814
Author's Phone Number:  (301) 657-3775
Author's Fax Number:    
Author's Net Address:   dunlop@inmet.inmet.com
-----------------------
Date Analyzed:          1991/01/15
Author of Analysis:     Doug Dunlop
Revision Number:        $Revision: 1.9 $
Date Last Revised:      $Date: 1995/08/03 17:59:37 $


Description of Problem
----------------------
Consider the following VHDL:

        ENTITY E IS
           GENERIC    (G1 : INTEGER   ; G2 : INTEGER := G1         );
           PORT       (P1 : STRING    ; P2 : STRING(P1'RANGE)      );
           PROCEDURE X(Y1, Y2: INTEGER; Y3 : INTEGER RANGE Y1 TO Y2);
        END E;

The generic interface list is apparently legal, but its meaning is not
defined.  At elaboration time, generics such as G1 and G2 take on values
by the elaboration of the associated generic map clause.  However, it is
not specified what order the elements in this association list are elaborated,
nor is it specified where in this association list the "implicit association
elements" are inserted for the default cases (see LRM 12.2.2).

The port interface list appears legal and well defined.

The parameter interface list appears legal, but seems to yield undefined
results at execution-time, since Y1 and Y2 do not have values when the
interface declaration for Y3 is elaborated (see LRM 12.5 Item 2).  Related to
this problem is whether and when default expressions on parameter interface
declarations get elaborated (I0066).

Note that Ada solves these kinds of problems by disallowing them.


Proposed Resolution
-------------------
For the time being, the implementation makes no promises
concerning these aspects of VHDL where the meaning is not defined by the
language.


VASG-ISAC Analysis & Rationale
------------------------------
(1) The simplest thing to do of course is to disallow a reference to a
formal from within its own interface list.  This is consistent with the
rules of Ada.

(2) Because Ada requires a type mark rather than a subtype indication in
an interface object declaration, there is more one could do in VHDL if a
reference to a formal from within its own interface list were allowed
(i.e., the reference could appear in a constraint).

(3) It would clearly improve the uniformity of the language if ports,
generics, and parameters were all treated consistently with respect to
this issue.

(4) VHDL plainly allows a generic (on an entity or block) to constrain
a port (on the same entity or block).  It is not clear what
other functionality along these lines users truly need.

(5) Reference to a formal parameter from within its own interface list
clearly implies an ordering on the way actual parameters are evaluated
and transmitted.  This may complicate the business of providing a
"foreign language" subprogram call capability.

(6) The present LRM requires that the generic clause be elaborated prior
to the corresponding generic map clause.  If reference to a generic
from within its own interface list is allowed, this seems somewhat
contradictory since evaluation of expressions in the map can be required
to create the generics (e.g., to get the size for a generic constrained
by a second generic).


VASG-ISAC Recommendation for IEEE Std 1076-1987
-----------------------------------------------
TBD


VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
TBD