VHDL Issue Number:      0101
Classification:         Language Definition Problem
Language Version:       VHDL-87
Summary:                Explicit type conversion between array types is ill-
                        defined.
Related Issues:         None.
Relevant LRM Sections:  7.3.5
Key Words and Phrases:  Type conversions, Array types.
Current Status:         ISAC-Approved
1076-1993 Disposition:  Closed (All Issues Completely Addressed)
Disposition Rationale:  Section 7.3.5 was revised.
Superseded By:          N/A
-----------------------
Date Submitted:         1988/05/10
Author of Submission:   Paul Menchini
Author's Affiliation:   CAD Language Systems, Inc.
Author's Post Address:  P.O. Box 13036
                        Research Triangle Park, NC  27709-3036
Author's Phone Number:  (919) 361-1913
Author's Fax Number:    
Author's Net Address:   mench@clsi.com
-----------------------
Date Analyzed:          1990/11/16
Author of Analysis:     Paul Menchini (mench@clsi.com)
Revision Number:        $Revision: 1.9 $
Date Last Revised:      $Date: 1995/08/03 18:14:23 $


Description of Problem
----------------------
There appears to be an error in the definition of the allowable explicit type
conversions between array types (LRM Section 7.3.5, Page 7-13).  One of the
enabling conditions is

        "for each index position, the index types are either the same
         or are convertible to each other;"

The use of the term convertible seems to imply implicit conversion as defined
in the paragraph immediately preceding the note at the end of this section.
However, implicit conversion in this paragraph is defined between *values*,
whereas the above condition requires conversion between *types*.

Moreover, the reflexivity requirement in the condition ("convertible to *each
other*"--emphasis mine) implies identity of the index subtypes, which is both
too restrictive and already explicitly identified in the first clause of the
condition.


Proposed Resolution
-------------------
Given these problems, I believe that the correct wording of the enabling
condition should be

        "for each index position, the index types are either the same
         or are closely related;"

Closely related types are defined in the portion of Section 7.3.5 starting with
the last paragraph on Page 7-12 through the end of the section.  Note that this
change makes the definition of closely related types recursive, which seems
appropriate.


VASG-ISAC Analysis & Rationale
------------------------------
The author is correct in his analysis and the ISAC favors his proposed
resolution.

During the next LRM rewrite, the notion of "closely related types" in paragraph
4 of Section 7.3.5 should be explicitly defined.  That is, the term should be
italicized and the material following this paragraph should be identified as
the definition of "closely related type."


VASG-ISAC Recommendation for IEEE Std 1076-1987
-----------------------------------------------
Adopt the author's proposed resolution.


VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
Change the wording of pargraph 4 of Section 7.3.5 as the author recommends.  In
addition, the introductory material of the paragraph should read approximately
as follows:

        Explicit type conversion is allowed between *closely related
        types*.  [The asterisks denote the beginning and end of
        italicized text.]  In particular, a type is closely related to
        itself.  Other types are closely related under the following
        conditions: ....