VHDL Issue Number:      0106
Classification:         Language Definition Problem
Language Version:       VHDL-87
Summary:                The signal updating steps of the simulation cycle is
                        incorrect.
Related Issues:         None.
Relevant LRM Sections:  12.6.3, 12.6.1, 12.6.2
Key Words and Phrases:  Simulation Cycle, implicit signals, explicit signals,
                        signal updating.
Current Status:         Submitted
1076-1993 Disposition:  Superseded (ISAC Issues Outstanding)
Disposition Rationale:  N/A
Superseded By:          1019
-----------------------
Date Submitted:         1991/02/19
Author of Submission:   Paul Menchini
Author's Affiliation:   CAD Language Systems, Inc.
Author's Post Address:  P.O. Box 13036
                        Research Triangle Park, NC  27709-3036
Author's Phone Number:  (919) 361-1913
Author's Fax Number:    
Author's Net Address:   mench@clsi.com
-----------------------
Date Analyzed:          TBD
Author of Analysis:     TBD
Revision Number:        $Revision: 1.9 $
Date Last Revised:      $Date: 1995/05/13 19:34:42 $


Description of Problem
----------------------
Section 12.6.3 describes the signal updating steps of the simulation cycle in
Items 2 and 3 of paragraph 4 (on page 12-14) as follows:

    2.  Each active explicit signal in the model is updated.  (Events
        may occur on signals as a result.) 

    3.  Each implicit signal in the model is updated.  (Events may occur
        on signals as a result.)

Consider this ordering of signal evaluation in light of the following example:

        entity E is
        end E;

        architecture A of E is
          component Buf
            port (I: in  Boolean;
                  O: out Boolean);
          end component;

          signal S1, S2: Boolean;
        begin
          process
          begin
            for i in 1 to 10 loop
              S1 <= False, True after 5 nS;
              wait for 10 nS;
            end loop;
            wait;
          end process;

          What_in_the_world: Buf port map (I => S1'stable, O => S2);
        end A;

        entity Buf is
          port (I: in  Boolean;
                O: out Boolean);
        end Buf;

        architecture Untimed of Buf is
        begin
          O <= I;
        end Untimed;

In this example a port (an explicit signal) is associated with an implicit
signal.  Therefore, the port cannot be evaluated until the implicit signal is
evaluated.


Proposed Resolution
-------------------
The signal updating algorithms described in Sections 12.6.1 and 12.6.2 are
correct with respect to the required order of signal evaluation.  Ignore the
bifurcated signal updating algorithm described in Section 12.6.3.


VASG-ISAC Analysis & Rationale
------------------------------
TBD


VASG-ISAC Recommendation for IEEE Std 1076-1987
-----------------------------------------------
TBD


VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
TBD