VASG Issue Number:      0110
Comment Author:         Paul Menchini
Comment Number:         01
Comment Date:           1991/03/21 (revised)

[This comment is based on a conversation between Oz Levia and myself, in which
we discussed his write-up of this issue.]

We were in agreement that ensuring that the mapping between a given library
logical name and its physical manifestation remains unchanged during and
between analyses is, in general, impossible.

In discussing this issue further, we decided that implementations are not
required to check the full mapping between the logical and physical, but can
*define* under what circumstances the mapping is considered to have changed.
For example, an implementation can store details about the time of analysis and
the identity of libraries in the library unit created by an analysis and use
this information (albeit imperfectly) to detect changes in the mapping of
libraries.  (The mapping of library logical names to physical libraries, and
therefore the definition of the circumstances under which the mapping changes,
are both outside of the scope of VHDL, so the LRM needn't define when the
mapping changes.)

Given that an implementation can define when the mapping of library logical
names to physical libraries changes, it can therefore detect the occurrence of
a change.  Thus the LRM can make use of this fact.  We discussed two
alternatives:

    1.  The LRM can allow (but not require) an implementation to detect when a
        library changes during the analysis of a design unit or between the
        analysis of a primary unit and (one of) its corresponding secondary
        units.  The implementation is free to issue some message decrying this
        change.

        This alternative is what is discussed in the issue write-up.

    2.  The LRM can require an implementation to detect when a library changes
        during the analysis of a design unit or between the analysis of a
        primary unit and (one of) its corresponding secondary units.  The
        implementation is then required to issue an error message if this
        situation occurs.

        This is the issue author's preferred solution.

We think that either situation is implementable, both in the LRM and in VHDL
tools.