VHDL Issue Number: 0112 Classification: Language Definition Problem Language Version: VHDL-87 Summary: No way to denote the region of a generate statement with the prefix of an expanded name. Related Issues: ? Relevant LRM Sections: 6.4, 10.1 Key Words and Phrases: Expanded name, selected name, generate statement, declarative region Current Status: Submitted 1076-1993 Disposition: Closed (All Issues Completely Addressed) Disposition Rationale: LRM is clear now, last para. of 6.4. Superseded By: N/A ----------------------- Date Submitted: 1988/07/07 Author of Submission: Paul Menchini Author's Affiliation: CAD Language Systems, Inc. Author's Post Address: P.O. Box 13036 Research Triangle Park, NC 27709-3036 Author's Phone Number: (919) 361-1913 Author's Fax Number: Author's Net Address: mench@clsi.com ----------------------- Date Analyzed: TBD Author of Analysis: TBD Revision Number: $Revision: 1.9 $ Date Last Revised: $Date: 1995/05/13 19:34:42 $ Description of Problem ---------------------- The last paragraph of Section 6.4 allows the prefix of an expanded name to denote "... a construct that is an entity, an architecture, a subprogram, a block statement, a process statement, or a loop statement, ...." Note that generate statements are not included. However, one of the changes made to 1076/B at the end of the standardization process was making the generate statement a declarative region, necessitating the ability to denote a generate statement with the prefix of an expanded name. Proposed Resolution ------------------- Add generate statements to the list of entities in Sections 6.4 and to the list of declarative regions in Section 10.1. VASG-ISAC Analysis & Rationale ------------------------------ TBD VASG-ISAC Recommendation for IEEE Std 1076-1987 ----------------------------------------------- TBD VASG-ISAC Recommendation for Future Revisions --------------------------------------------- TBD