VHDL Issue Number: 0113 Classification: Language Definition Problem Language Version: VHDL-87 Summary: Scope of expanded names is unclear. Related Issues: None. Relevant LRM Sections: 6.3, 10.1, 10.3 Key Words and Phrases: Expanded names, selected names, declarative regions, secondary units Current Status: ISAC-Approved 1076-1993 Disposition: Superseded (ISAC Issues Outstanding) Disposition Rationale: Superseded By: 1057 ----------------------- Date Submitted: 1988/07/07 Author of Submission: Paul Menchini Author's Affiliation: CAD Language Systems, Inc. Author's Post Address: P.O. Box 13036 Research Triangle Park, NC 27709-3036 Author's Phone Number: (919) 361-1913 Author's Fax Number: Author's Net Address: mench@clsi.com ----------------------- Date Analyzed: 1991/01/22 Author of Analysis: Doug Dunlop Revision Number: $Revision: 1.9 $ Date Last Revised: $Date: 1995/05/13 19:34:42 $ Description of Problem ---------------------- It is unclear where certain expanded names are legal. To illustrate, consider the following design units: entity E is port (P: in bit); end E; architecture A of E is signal Q: bit; begin ... E.P ...; -- which of these expanded names are legal? ... A.Q ...; ... E.Q ...; ... A.P ...; end A; The LRM makes two different, but similar, statements regarding expanded names. The first, in Section 6.3, states: "An expanded name denotes an entity declared immediately within a named construct if the prefix denotes a construct that is an entity, an architecture, ..., and the suffix is the simple name, character literal, or operator symbol of an entity whose declaration occurs immediately within that construct. This form of expanded name is only allowed within the construct itself." Using a strict interpretation, the name E.Q is not legal because Q is not declared within the named construct E. Also the name A.P is not legal because the declaration of P is not within A. However, consider the following statement, in Section 10.3, page 10-4 of the LRM: "Finally, within the declarative region associated with a construct other than a record type declaration, any declaration that occurs immediately within the region is visible by selection at the place of the suffix of an expanded name whose prefix denotes the construct." However, the legality of the names is not obvious because the entity declaration together with the architecture body form a single declarative region (Section 10.1). How is the declarative region denoted? Can either E or A denote the entire region or does each denote a part of it? I have been informed by the language designers that the intent was for at least E.P and A.Q to be legal. Proposed Resolution ------------------- Allow only E.P and A.Q in the above example to be valid. VASG-ISAC Analysis & Rationale ------------------------------ The language problem described above is genuine. The quoted sentence from LRM 6.3 seems to be the defining rule for expanded names and seems relatively clear. The sentence makes use of the terms "construct" and not "declarative region". The problem sentence is the one quoted from LRM 10.3 since it does not deal with the case where multiple "constructs" or associated with a declarative region. It seems to the ISAC that the most natural interpretation here is to require the entity name prefix for those items declared within the entity and the architecture name prefix for those items declared within the architecture body. This interpretation matches the proposed resolution given above. VASG-ISAC Recommendation for IEEE Std 1076-1987 ----------------------------------------------- The use of an expanded name to reference an item declared immediately within an entity declaration must use the entity name as a prefix. Similarly, the use of an expanded name to reference an item declared immediately within an architecture body must use the architecture name as a prefix. VASG-ISAC Recommendation for Future Revisions --------------------------------------------- Revise the quoted sentence from LRM 10.3 to reflect this interpretation.