VHDL Issue Number:      0118
Classification:         Terminology, Grammar, and Typographical Errors
Language Version:       VHDL-87
Summary:                Referring to the ancient term "NETS" instead of
                        "SIGNALS."
Related Issues:         None.
Relevant LRM Sections:  12, 12.1
Key Words and Phrases:  Signals
Current Status:         Analyzed
1076-1993 Disposition:  Closed (All Issues Completely Addressed)
Disposition Rationale:  Section 12 was updated.
Superseded By:          N/A
-----------------------
Date Submitted:         1989/06/21
Author of Submission:   Ken Scott
Author's Affiliation:   Vantage Analysis Systems, Inc.
Author's Post Address:  42840 Christy St., Suite 201
                        Fremont, CA   94538
Author's Phone Number:  (415) 659-0901
Author's Fax Number:    
Author's Net Address:   N/A
-----------------------
Date Analyzed:          1991/03/21
Author of Analysis:     Alex Zamfirescu
Revision Number:        $Revision: 1.9 $
Date Last Revised:      $Date: 1995/08/03 18:44:35 $


Description of Problem
----------------------
In the 3rd paragraph of chapter 12, and the 1st paragraph of chapter 12.1, the
LRM refers to a term "NETS" which is no longer defined in the LRM.


Proposed Resolution
-------------------
This should be replaced by the term "SIGNALS."


VASG-ISAC Analysis & Rationale
------------------------------
Indeed the nets are not defined in the LRM.  However, the term "net" or "nets"
appears in more places in the LRM.  First in the final note of the LRM 4.3.1.2
Signal Declaration:

     Signals are given initial values by initializing their drivers;
     the initial values of drivers are then propagated through the
                      (1
     corresponding net   to determine the initial values of the signals
                         (2
     that make up the net  (see Section 12.6.3).

Second, in Chapter 12:
                           (3
     Initialization of nets in the model then occurs.  Finally, simulation
     of the model proceeds. Simulation consists of the repetitive execution
                                                                          (4
     of the simulation cycle, during which processes are executed and nets
     updated.

and also in LRM 12.1, Elaboration of a Design Hierarchy:

     The elaboration of a design hierarchy creates a collection of processes
                           (5                                       (6
     interconnected by nets  ; this collection of processes and nets can then
     be executed to simulate the behavior of the design.

The use of "net" in 1) may be replaced by "set of connected signals" while 2)
is replaced by "set."  Appearances 3) and 4) above may be replaced by
"signals", and apparitions 5) and 6) above may be replaced by "connected
signals."


VASG-ISAC Recommendation for IEEE Std 1076-1987
-----------------------------------------------
Replace the final note of the LRM 4.3.1.2 Signal Declaration:

     Signals are given initial values by initializing their drivers;
     the initial values of drivers are then propagated through the
     corresponding net to determine the initial values of the signals
     that make up the net  (see Section 12.6.3).

by:

     Signals are given initial values by initializing their drivers;
     the initial values of drivers are then propagated through the
     corresponding set of connected signals to determine the initial
     values of the signals that make up that set  (see Section 12.6.3).

Replace (in Chapter 12):

     Initialization of nets in the model then occurs.  Finally, simulation
     of the model proceeds. Simulation consists of the repetitive execution
     of the simulation cycle, during which processes are executed and nets
     updated.

by:

     Initialization of signals in the model then occurs.  Finally, simulation
     of the model proceeds. Simulation consists of the repetitive execution
     of the simulation cycle, during which processes are executed and signals
     updated.

Replace (in LRM 12.1, Elaboration of a Design Hierarchy):

     The elaboration of a design hierarchy creates a collection of processes
     interconnected by nets; this collection of processes and nets can then
     be executed to simulate the behavior of the design.

by:

     The elaboration of a design hierarchy creates a collection of processes
     interconnected by connected signals; this collection of processes and
     connected signals can then be executed to simulate the behavior of the
     design.


VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
Insert this language in the LRM.