VHDL Issue Number: 0119 Classification: Language Definition Problem Language Version: VHDL-87 Summary: "Conditional" used when "concurrent" is meant. Related Issues: None. Relevant LRM Sections: 9.5, 8.3.1 Key Words and Phrases: Concurrent Signal Assignment Statement, Conditional Signal, Assignment Statement, Transport Delay Model Current Status: ISAC-Approved 1076-1993 Disposition: Closed (All Issues Completely Addressed) Disposition Rationale: Section 9.5 was updated. Superseded By: N/A ----------------------- Date Submitted: 1989/06/21 Author of Submission: Ken Scott Author's Affiliation: Vantage Analysis Systems, Inc. Author's Post Address: 42840 Christy St., Suite 201 Fremont, CA 94538 Author's Phone Number: (415) 659-0901 Author's Fax Number: Author's Net Address: N/A ----------------------- Date Analyzed: 1990/10/08 Author of Analysis: Chuck Swart Revision Number: $Revision: 1.9 $ Date Last Revised: $Date: 1995/08/03 18:45:35 $ Description of Problem ---------------------- In the 7th paragraph of chapter 9.5, this statement is restricting the translation of 'transport' signal assignments to only conditional signal assignments: "If the option transport appears in the CONDITIONAL signal assignment, then the reserved word transport appears in every signal assignment statement in the process statement;" Proposed Resolution ------------------- If you replace 'conditional' with 'concurrent', you get the desired meaning: "If the option transport appears in the CONCURRENT signal assignment, then the reserved word transport appears in every signal assignment statement in the process statement;" VASG-ISAC Analysis & Rationale ------------------------------ The author's analysis is correct. VASG-ISAC Recommendation for IEEE Std 1076-1987 ----------------------------------------------- The above re-wording of the paragraph should be assumed. VASG-ISAC Recommendation for Future Revisions --------------------------------------------- The above re-wording of the paragraph should be included.