VHDL Issue Number:      0131
Classification:         Language Definition Problem
Language Version:       VHDL-87
Summary:                Default binding rules fail to consider entity 
                        visibility.
Related Issues:
Relevant LRM Sections:  5.2
Key Words and Phrases:  Entity Aspect, Binding Indication
Current Status:         Superseded
1076-1993 Disposition:  Closed (All Issues Completely Addressed)
Disposition Rationale:  Already superseded.
Superseded By:          N/A
-----------------------
Date Submitted:         1989/06/21
Author of Submission:   Rod Farrow
Author's Affiliation:   Vantage Analysis Systems, Inc.
Author's Post Address:  42840 Christy St., Suite 201
                        Fremont, CA   94538
Author's Phone Number:  (415) 659-0901
Author's Fax Number:    
Author's Net Address:   N/A
-----------------------
Date Analyzed:          1991/01/22
Author of Analysis:     Doug Dunlop
Revision Number:        $Revision: 1.7 $
Date Last Revised:      $Date: 1995/05/13 19:34:42 $


Description of Problem
----------------------
In the default entity_aspect for a default binding_indication, the default
entity (if none is specified) is defined to be any visible entity with the same
simple name as that of the component being instantiated.  However, in nearly
all cases that simple name will already be associated with a component (the
name of the component being instantiated) and will not be the name of a visible
entity.


Proposed Resolution
-------------------
We propose that the default entity be defined as "work.name" instead of
simply "name".


VASG-ISAC Analysis & Rationale
------------------------------
This issue is considered in IR-0048, which see.


VASG-ISAC Recommendation for IEEE Std 1076-1987
-----------------------------------------------
See IR-0048.


VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
See IR-0048.