VHDL Issue Number:      0133
Classification:         Language Definition Problem
Language Version:       VHDL-87
Summary:                The rules for conformance of forward declarations are
                        overly restrictive.
Related Issues:         
Relevant LRM Sections:  2.7
Key Words and Phrases:  Conformance Rules
Current Status:         Submitted
1076-1993 Disposition:  Bugs Fixed, Enhancements Outstanding (No ISAC Issues)
Disposition Rationale:  Non-ISAC issues outstanding.
Superseded By:          N/A
-----------------------
Date Submitted:             1989/06/21
Author of Submission:   Rod Farrow
Author's Affiliation:   Vantage Analysis Systems, Inc.
Author's Post Address:  42840 Christy St., Suite 201
                        Fremont, CA   94538
Author's Phone Number:  (415) 659-0901
Author's Fax Number:    
Author's Net Address:   N/A
-----------------------
Date Analyzed:          TBD
Author of Analysis:     TBD
Revision Number:        $Revision: 1.9 $
Date Last Revised:      $Date: 1995/08/04 01:37:53 $


Description of Problem
----------------------
   The rules for conformance of forward declarations (section 2.7) are 
   overly restrictive, for instance the examples given.  The variations that 
   the other language rules identify as equivalent should be allowed.  These 
   include: 
     1. A parameter with default mode vs. one with an explicit mode 
        that is the same value as the default.
     2. "X,Y:T" vs "X:T;Y:T".  

Proposed Resolution
-------------------
   We propose that these restrictions be relaxed to allow these extra cases.

VASG-ISAC Analysis & Rationale
------------------------------


VASG-ISAC Recommendation for IEEE Std 1076-1987
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VASG-ISAC Recommendation for Future Revisions
---------------------------------------------