VHDL Issue Number: 0138 Classification: Enhancement Request Language Version: VHDL-87 Summary: Restrict formal designators to be either a simple name or a function whose lone argument is a simple name. Related Issues: Relevant LRM Sections: 4.3.1.2 Key Words and Phrases: Formal Designator Current Status: Submitted 1076-1993 Disposition: Bugs Fixed, Enhancements Outstanding (No ISAC Issues) Disposition Rationale: Non-ISAC issues outstanding. Superseded By: N/A ----------------------- Date Submitted: 1989/06/21 Author of Submission: Rod Farrow Author's Affiliation: Vantage Analysis Systems, Inc. Author's Post Address: 42840 Christy St., Suite 201 Fremont, CA 94538 Author's Phone Number: (415) 659-0901 Author's Fax Number: Author's Net Address: N/A ----------------------- Date Analyzed: TBD Author of Analysis: TBD Revision Number: $Revision: 1.9 $ Date Last Revised: $Date: 1995/08/04 01:37:53 $ Description of Problem ---------------------- We propose that formal designators be restricted to being either a simple name or a function whose lone argument is a simple name. This restriction will not eliminate any essential functionality from the language. At the same time, it will make the language more effective from a documentation standpoint, and easier to implement. Proposed Resolution ------------------- We propose that formal designators be restricted to being either a simple name or a function whose lone argument is a simple name. This restriction will not eliminate any essential functionality from the language. At the same time, it will make the language more effective from a documentation standpoint, and easier to implement. VASG-ISAC Analysis & Rationale ------------------------------ VASG-ISAC Recommendation for IEEE Std 1076-1987 ----------------------------------------------- VASG-ISAC Recommendation for Future Revisions ---------------------------------------------