VHDL Issue Number: 0141 Classification: Language Definition Problem Language Version: VHDL-87 Summary: What should happen when there is a port clause in a block statement but no port map clause? Related Issues: ? Relevant LRM Sections: 9.1, 12.2 Key Words and Phrases: Generic map clause, port map clause Current Status: Submitted 1076-1993 Disposition: Superseded (ISAC Issues Outstanding) Disposition Rationale: N/A Superseded By: 1029 ----------------------- Date Submitted: 1989/06/21 Author of Submission: Ken Scott Author's Affiliation: Vantage Analysis Systems, Inc. Author's Post Address: 42840 Christy St., Suite 201 Fremont, CA 94538 Author's Phone Number: (415) 659-0901 Author's Fax Number: Author's Net Address: N/A ----------------------- Date Analyzed: TBD Author of Analysis: TBD Revision Number: $Revision: 1.9 $ Date Last Revised: $Date: 1995/07/26 19:27:54 $ Description of Problem ---------------------- The second paragraph of section 12.2.1 indicates explicitly what should happen in the absence of a generic map clause: The value of a generic constant is not defined until a subsequent generic map clause is evaluated, or in the absence of a generic map clause, until the default expression associated with the generic constant is evaluated to determine the value of the constant. There is no corresponding passage in section 12.2.3 for port maps. The LRM does not explicitly state what happens in the absence of an explicit port map clause. Proposed Resolution ------------------- Section 12.2.3 should be updated with a description of what to do when a port map clause is absent. VASG-ISAC Analysis & Rationale ------------------------------ VASG-ISAC Recommendation for IEEE Std 1076-1987 ----------------------------------------------- VASG-ISAC Recommendation for Future Revisions ---------------------------------------------