VHDL Issue Number:      0142
Classification:         Language Clarification
Language Version:       VHDL-87
Summary:                The 'note' implies that predefined attributes
                        of the actual will not be visible on the formal.
Related Issues:         ?
Relevant LRM Sections:  2.1.1
Key Words and Phrases:  User-defined attributes, Pre-defined attributes
Current Status:         Submitted
1076-1993 Disposition:  Superseded (ISAC Issues Outstanding)
Disposition Rationale:  ??
Superseded By:          1020
-----------------------
Date Submitted:         1989/06/21
Author of Submission:   Howard Gebb, Ken Scott
Author's Affiliation:   Vantage Analysis Systems, Inc.
Author's Post Address:  42840 Christy St., Suite 201
                        Fremont, CA   94538
Author's Phone Number:  (415) 659-0901
Author's Fax Number:    
Author's Net Address:   N/A
-----------------------
Date Analyzed:          TBD
Author of Analysis:     TBD
Revision Number:        $Revision: 1.9 $
Date Last Revised:      $Date: 1995/05/13 21:53:48 $


Description of Problem
----------------------
   The note at the bottom of section 2.1.1 really only applies to
   user-defined attributes.  For predefined attributes, there needs
   to be some mechanism for communicating the information from the
   actual to the formal.  For example, when referring to the attribute
       'EVENT
   the mechanism by which the formal obtains the same value as the actual
   is not defined by the language.

Proposed Resolution
-------------------
   Either clarify the note to only refer to user-defined attributes,
   or specify an explicit mechanism by which predefined attributes
   on actuals are propagated down to the formals.

VASG-ISAC Analysis & Rationale
------------------------------


VASG-ISAC Recommendation for IEEE Std 1076-1987
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VASG-ISAC Recommendation for Future Revisions
---------------------------------------------