VHDL Issue Number:      0145
Classification:         Language Definition Problem
Language Version:       VHDL-87
Summary:                Are recursive configurations legal?
Related Issues:         None.
Relevant LRM Sections:  10.3, 11.1
Key Words and Phrases:  Configuration Declaration, Visibility, Design Unit
Current Status:         Submitted
1076-1993 Disposition:  Unknown
Disposition Rationale:  ??
Superseded By:          N/A
-----------------------
Date Submitted:             1989/06/22
Author of Submission:   Ken Scott
Author's Affiliation:   Vantage Analysis Systems, Inc.
Author's Post Address:  42840 Christy St., Suite 201
                        Fremont, CA   94538
Author's Phone Number:  (415) 659-0901
Author's Fax Number:    
Author's Net Address:   N/A
-----------------------
Date Analyzed:          TBD
Author of Analysis:     TBD
Revision Number:        $Revision: 1.8 $
Date Last Revised:      $Date: 1995/05/13 21:53:48 $


Description of Problem
----------------------
    Examine the following VHDL:
        ---------------------------------------------
        entity E is
           generic( N : positive );
           port   ( P : out BIT  );
        end E;
        ---------------------------------------------
        architecture A of E is
        begin
           G1 : if  (N > 1) generate
                   l:block
                        signal S : BIT;
                        component C generic(N : positive); port(P : out BIT);
                        end component;
                     begin
                        I:C generic map( N => N - 1 ) port map( P => S );
                        P <= not S;
                     end block;
                end generate;
           G2 : if  (N = 1) generate
                    P <= '0';
                end generate;
        end A;
        ---------------------------------------------
        configuration C1 of E is
           for A
               -- For generate G1.
               for G1
                  -- For block L.
                  for L
                      -- For component C.
                      for I : C use configuration C1; -- Is this legal?
                      end for;
                  end for;
               end for;
           end for;
        end C1;
        ---------------------------------------------

    - The intended meaning of this VHDL is for the configuration
      to be recursive and to elaborate the hierarchy of design
      entities until N has been decreased to zero.  This is a
      powerful concept, but it's not clear that the LRM allows it.

    - Relevant LRM sections are:
      10.3:  "A declaration is only visible within a certain part
              of its scope;  this part starts at the end of the
              declaration EXCEPT IN THE DECLARATION OF A DESIGN
              UNIT, IN WHICH CASE IT STARTS IMMEDIATELY AFTER THE
              RESERVED WORD 'IS' GIVEN AFTER THE IDENTIFIER OF THE
              DESIGN UNIT."
              -- Implication.  The identifier C1 should be directly
                 visible in the configuration.

      11.1:  "Analysis of a design unit DEFINES the corresponding
              library unit in a design library."
             -- Implication.  A design unit is not defined until
                it has been analyzed.

    The question is whether a primary unit needs to be defined in
    the design library before it can be used.

    This issue was discussed at the VASG-ISAC meeting in Fremont
    on 5/1 - 5/2/89.  No consensus was reached at that time.
          

Proposed Resolution
-------------------
    None supplied yet.  

VASG-ISAC Analysis & Rationale
------------------------------


VASG-ISAC Recommendation for IEEE Std 1076-1987
-----------------------------------------------


VASG-ISAC Recommendation for Future Revisions
---------------------------------------------