VHDL Issue Number:      0146
Classification:         Language Definition Problem
Language Version:       VHDL-87
Summary:                May resolution functions be overloaded?
Related Issues:         None.
Relevant LRM Sections:  2.3, 2.4, 10.5
Key Words and Phrases:  Overloading, Resolution Functions
Current Status:         Submitted
1076-1993 Disposition:  Closed (All Issues Completely Addressed)
Disposition Rationale:  Sections 4.2 and 10.5 were revised.
Superseded By:          N/A
-----------------------
Date Submitted:         1991/03/11
Author of Submission:   Paul Menchini
Author's Affiliation:   CAD Language Systems, Inc.
Author's Post Address:  P.O. Box 13036
                        Research Triangle Park, NC  27709-3036
Author's Phone Number:  (919) 361-1913
Author's Fax Number:    
Author's Net Address:   mench@clsi.com
-----------------------
Date Analyzed:          TBD
Author of Analysis:     TBD
Revision Number:        $Revision: 1.9 $
Date Last Revised:      $Date: 1995/08/04 01:39:21 $


Description of Problem
----------------------
May resolution functions be overloaded?  If so, can their parameter and result
type profile be used to disambiguate the name of a resolution function?
Section 10.5 may be interpreted to allow overloaded resolution functions, but
it is not explicit.


Proposed Resolution
-------------------
Allow resolution functions to be overloaded.  Allow the normal overload
resolution to disambiguate the name of a resolution function.

Specifically, add language (if necessary) or a note to Section 10.5 concerning
resolution functions.


VASG-ISAC Analysis & Rationale
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TBD


VASG-ISAC Recommendation for IEEE Std 1076-1987
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TBD


VASG-ISAC Recommendation for Future Revisions
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TBD