VHDL Issue Number:      0147
Classification:         Language Deficiencies and Modeling Problems
Language Version:       VHDL-87
Summary:                Assignment in the form of concatenation needed.
Related Issues:         0148
Relevant LRM Sections:  8.3, 8.4
Key Words and Phrases:  Assignment, Signal Assignment, Variable Assignment,
                        Concatenation
Current Status:         Submitted
1076-1993 Disposition:  Bugs Fixed, Enhancements Outstanding (No ISAC Issues)
Disposition Rationale:  Non-ISAC issues outstanding.
Superseded By:          N/A
-----------------------
Date Submitted:         1991/03/11
Author of Submission:   Paul Menchini
Author's Affiliation:   CAD Language Systems, Inc.
Author's Post Address:  P.O. Box 13036
                        Research Triangle Park, NC  27709-3036
Author's Phone Number:  (919) 361-1913
Author's Fax Number:    
Author's Net Address:   mench@clsi.com
-----------------------
Date Analyzed:          TBD
Author of Analysis:     TBD
Revision Number:        $Revision: 1.9 $
Date Last Revised:      $Date: 1995/08/04 01:39:21 $


Description of Problem
----------------------
The LRM allows the target of signal and variable assignment statements in the
form of an aggregate.  However, there are times when assignment in the form of
a concatenation is more desirable.  By way of an example, consider the
following VHDL fragment:

                :
        subtype Word is Bit_Vector (31 downto 0);
        subtype Extended_Word is Bit_Vector (32 downto 0);

        function "+" (L, R: Word) return Extended_Word;
                :
                :
        signal A, B, Sum: Word;
        signal Carry: Bit;
                :
                :
        (Carry, Sum) <= A + B;  -- Wrong!
                :

What is desired is "Carry & Sum <= A + B;"; currently, the only workaround is
to use an intermediate signal or to redefine "+".

Note, the concept of targets in the form of concatenations was adapted from
ISPS.  However, in ISPS the semantics are not of aggregation, but of
concatentation.


Proposed Resolution
-------------------
TBD


VASG-ISAC Analysis & Rationale
------------------------------
TBD


VASG-ISAC Recommendation for IEEE Std 1076-1987
-----------------------------------------------
TBD


VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
TBD