VHDL Issue Number: 0149 Classification: Terminology, Grammar, and Typographical Errors Language Version: VHDL-87 Summary: More typographical and editorial errors. Related Issues: 0002 Relevant LRM Sections: 1.3, 1.3.1, 2.1.1.1, 2.1.1.2, 2.3, 2.3.1, 2.5, 2.7, 3.1.1.1, 3.1.3, 3.2.1, 3.3.1, 4.1, 4.3.1.2, 4.3.1.3, 4.3.3, 4.3.4, 4.4, 5.1, 5.2.1.2, 6.5, 6.6, 7.3.2.2, 7.3.6, 8.3.1, 8.4, 8.7, 9.1, 9.3, 9.4, 9.6, 10.4, 11.2, 12.3.1.4, 12.6.1, 12.6.3, 13.1, 13.2, 13.4.1, 13.7, 13.10, 14.1, 14.3, Appendix A Key Words and Phrases: N/A Current Status: Submitted 1076-1993 Disposition: Superseded (ISAC Issues Outstanding) Disposition Rationale: Superseded By: 1030 ----------------------- Date Submitted: 1991/03/12 Author of Submission: Paul Menchini (and many others) Author's Affiliation: CAD Language Systems, Inc. Author's Post Address: P.O. Box 13036 Research Triangle Park, NC 27709-3036 Author's Phone Number: (919) 361-1913 Author's Fax Number: Author's Net Address: mench@clsi.com ----------------------- Date Analyzed: TBD Author of Analysis: TBD Revision Number: $Revision: 1.9 $ Date Last Revised: $Date: 1995/05/13 19:34:42 $ Description of Problem ---------------------- There are a number of typographical and editorial errors in the LRM in addition to those collected in Issue Report 0002. These are described below. 1. Sentence 2 of paragraph 1 of Section 5.2.1.2 reads: Similarly, a port map aspect associates signals with the formal ports of block. It should read: Similarly, a port map aspect associates signals with the formal ports of *a* block. [Emphasis mine, and not to be included in the LRM.] 2. On page 7-11, item 6 of paragraph 3 of Section 7.3.2.2 refers to "initialization specification"s, which of course are an artifact of previous versions of VHDL. This item should be deleted and the word "signal" added to "constant or variable object" in item 5 of the same paragraph. 3. The last item on page A-4 indicates that the production for component_specification is from Section 5.3. It is actually from Section 5.2. 4. Paragraph 3 of section 12.6.3 (on page 12-14) contains the sentence: At the beginning of simulation, current time is assumed to be 0ns. There is no space between the abstract literal and the unit in the physical literal. 5. The header "Examples::" within Section 2.3 contains (as shown) two colons. 6. The headers "Note:" within Sections 1.3, 1.3.1, 2.1.1.1, 2.1.1.2, 2.3, 2.3.1, 2.5, 2.7, 3.1.1.1, 3.1.3, 3.2.1, 4.1, 4.3.1.2, 4.3.1.3, 4.3.3, 4.4, 5.1, 7.3.6, 8.3.1, 8.4, 8.7, 9.1, 9.3, 9.4, 9.6, 10.4, 11.2, 12.3.1.4, 12.6.1, 12.6.3, 13.1, 13.2, 13.10, 14.1, and 14.3 are singular although there are multiple notes. 7. The second-to-last sentence of the "out" item in paragraph 11 of Section 4.3.3 (on page 4-10) states "For a file object, operation ENDFILE is allowed." Because of the resolution of Issue Report 0032, ENDFILE is not applicable to file objects of mode out. This sentence is therefore meaningless and should be stricken. 8. The last sentence of the "inout" item in paragraph 11 of Section 4.3.3 states "For a file object, operation ENDFILE is allowed." However, there are no file objects of mode inout, so this sentence is meaningless. 9. The first sentence of Section 4.3.4 refers to "existing object." The term "existing object" is not defined, although object is. The word "existing" appears to be a noise word that conveys nothing and indeed might be confusing. It should be deleted. 10. The example "OUTPUT'FANOUT" of Section 6.6 is potentially confusing and should be modified. There is no language-based way to compute the fanout of an output port in VHDL. 11. The note in Section 6.5 states "If A is a one-dimensional array of objects ...." The reference to "of objects" is misleading and should be deleted. A may be an access value whose designated type is a one-dimensional array or a nulladic function that returns an array or an access value whose designated type is a one-dimensional array. 12. The third note of Section 12.6.1 states "... if S is a local signal appearing in a port association list, the driving value of S can only be obtained after the driving value of the corresponding actual part is computed." The word "formal" should be substituted for "actual", since S (being a *local* signal) is the actual. 13. The types PART and WIRE from the examples of Section 3.3.1 (on page 3-15) read: type PART is record PART_NAME : STRING; CONNECTIONS : WIRE_LIST_PTR; end record; type WIRE is record WIRE_NAME : STRING; CONNECTS : PART_LIST_PTR; end record; The use of unconstriained arrays as record elements is illegal. The types should therefore read: constant PART_NAME_LENGTH: Positive := ...; constant WIRE_NAME_LENGTH: Positive := ...; type PART is record PART_NAME : STRING (1 to PART_NAME_LENGTH); CONNECTIONS : WIRE_LIST_PTR; end record; type WIRE is record WIRE_NAME : STRING (1 to WIRE_NAME_LENGTH); CONNECTS : PART_LIST_PTR; end record; 14. The Examples of Sections 3.1.3, 3.2.1, 4.3.1.2, 5.1, 6.5, and 13.4.1 precede the Notes. In other sections, the Notes precede the Examples. 15. The Examples of Section 13.7 have a singular header and are not separated by blank lines, as is true of other examples. 16. The right-hand side of the production for "block_statement" in Section 9.1 (on page 9-2) is improperly indented. The production should appear as follows: block_statement ::= *block*_label : BLOCK [ ( *guard*_expression ) ] block_header block_declarative_part BEGIN block_statement_part END BLOCK [ *block*_label ] ; Proposed Resolution ------------------- These should be corrected. VASG-ISAC Analysis & Rationale ------------------------------ TBD VASG-ISAC Recommendation for IEEE Std 1076-1987 ----------------------------------------------- TBD VASG-ISAC Recommendation for Future Revisions --------------------------------------------- TBD