VHDL Issue Number:      0152
Classification:         Language Deficiencies and Modeling Problems
Language Version:       VHDL-87
Summary:                Case statement ranges must be scalar
Related Issues:         None.
Relevant LRM Sections:  8.7, 3.1
Key Words and Phrases:  Case statement, choices, ranges
Current Status:         Submitted
1076-1993 Disposition:  Bugs Fixed, Enhancements Outstanding (No ISAC Issues)
Disposition Rationale:  Non-ISAC issues outstanding.
Superseded By:          N/A
-----------------------
Date Submitted:         1991/03/12
Author of Submission:   Paul Menchini
Author's Affiliation:   CAD Language Systems, Inc.
Author's Post Address:  P.O. Box 13036
                        Research Triangle Park, NC  27709-3036
Author's Phone Number:  (919) 361-1913
Author's Fax Number:    
Author's Net Address:   mench@clsi.com
-----------------------
Date Analyzed:          TBD
Author of Analysis:     TBD
Revision Number:        $Revision: 1.9 $
Date Last Revised:      $Date: 1995/08/04 01:42:22 $


Description of Problem
----------------------
The selector expression in a case statement may be either of a discrete type or
of a one-dimensional character array type.  When the selector expression is of
a discrete type, the choices in the case statement alternatives may be
individual choices, groups of choices, or ranges:

        case <some integer expression> is
          when 1        => ...;
          when 2 | 5    => ...;
          when 17 to 42 => ...;
          when others   => ...;
        end case;

However, when the selector expression is of a one-dimensional character array
type, the choices in the case statement alternatives may *not* be ranges:

        subtype three_bit is Bit_Vector (1 to 3);
        variable V: three_bit;
            :
        case V is
          when "000"            => ...;
          when "001" | "010"    => ...;
          when "011" to "111"   => ...;         -- Illegal!
        end case;

The reason that this range is illegal is that the first sentence of the second
paragraph of Section 3.1 states "A range specifies a subset of values *of a
scalar type*."  [Emphasis mine.]

This is a reasonable restriction in Ada and VHDL 7.2, from whence this
restriction comes, as both insist that the selector expressions of case
statements be discrete types.

When the ability to have the selector expression be of a one-dimensional
character array type was added to 1076, the appropriate relaxation of this
restriction was likely overlooked.

One difficulty in relaxing this restriction is whether the leftmost component
of the range varies fastest or the rightmost component does.  In other words,
does the range "011" to "111" mean the same as the sequence "011" | "111"?  Or
does it mean "011" | "100" | "101" | "110" | "111"?


Proposed Resolution
-------------------
Relax the restriction that ranges in the choices of case statement alternatives
must be discrete.  Declare that (consistent with multi-level aggregates),
arrays are row-major.  Thus, the range "011" to "111" means that same as the
sequence "011" | "100" | "101" | "110" | "111".


VASG-ISAC Analysis & Rationale
------------------------------
TBD


VASG-ISAC Recommendation for IEEE Std 1076-1987
-----------------------------------------------
TBD


VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
TBD