VHDL Issue Number:      0156
Classification:         Language Definition Problem
Language Version:       VHDL-87
Summary:                May analyzers make non-locally static checks?
Related Issues:         None.
Relevant LRM Sections:  11.4
Key Words and Phrases:  Analysis, errors
Current Status:         Submitted
1076-1993 Disposition:  Superseded (ISAC Issues Outstanding)
Disposition Rationale:  N/A
Superseded By:          1032
-----------------------
Date Submitted:         1991/03/13
Author of Submission:   Paul Menchini
Author's Affiliation:   CAD Language Systems, Inc.
Author's Post Address:  P.O. Box 13036
                        Research Triangle Park, NC  27709-3036
Author's Phone Number:  (919) 361-1913
Author's Fax Number:    
Author's Net Address:   mench@clsi.com
-----------------------
Date Analyzed:          TBD
Author of Analysis:     TBD
Revision Number:        $Revision: 1.9 $
Date Last Revised:      $Date: 1995/08/04 01:42:22 $


Description of Problem
----------------------
The LRM does not state when certain checks can or must be made during the
processing of a VHDL design file.  However, there is a clear implication that
there are at least four phases:  (1) Analysis.  (2) Static model elaboration.
(3) Model initialization.  (4) Model execution.  These phases are used
extensively in Chapters 10, 11, and 12, and less so in the rest of the LRM.

Given these processing steps, can analysis tools make checks (e.g., and
especially, subtype checks) that often cannot be made until subsequent steps?

Specifically, what exactly does the word "any" mean in paragraph 3 of Section
11.4:

        If any error is detected while attempting to analyze a design
        unit, then the attempted analysis is rejected and has no effect
        whatsoever on the current working library.

Does this sentence mean that the design unit will not be placed in library Work
if any errors which must be detected during analysis are in fact present?  Or
does it allow errors that can be detected during analysis but are not required
to be detected until later (that in fact would occur later) to prevent the
design unit from being placed in library Work.


Proposed Resolution
-------------------
Allow all tools to detect errors as soon as is possible.  This proposal is
consistent with good human-engineering principles.


VASG-ISAC Analysis & Rationale
------------------------------
TBD


VASG-ISAC Recommendation for IEEE Std 1076-1987
-----------------------------------------------
TBD


VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
TBD