VHDL Issue Number:      0163
Classification:         Language Definition Problem
Language Version:       VHDL-87
Summary:                When do buffer ports have sources?
Related Issues:         None.
Relevant LRM Sections:  4.3.1.2
Key Words and Phrases:  Buffer ports, sources, association, scalar signals,
                        composite signals, component instances,
                        binding indication
Current Status:         Submitted
1076-1993 Disposition:  Superseded (ISAC Issues Outstanding)
Disposition Rationale:  N/A
Superseded By:          1068
-----------------------
Date Submitted:         1991/03/14
Author of Submission:   Paul Menchini
Author's Affiliation:   CAD Language Systems, Inc.
Author's Post Address:  P.O. Box 13036
                        Research Triangle Park, NC  27709-3036
Author's Phone Number:  (919) 361-1913
Author's Fax Number:    
Author's Net Address:   mench@clsi.com
-----------------------
Date Analyzed:          TBD
Author of Analysis:     TBD
Revision Number:        $Revision: 1.10 $
Date Last Revised:      $Date: 1995/05/13 21:53:48 $


Description of Problem
----------------------
Consider the following VHDL:

        entity E is
          port (P: buffer integer := 100);
        end E;

        architecture A of E is
        begin
          assert P = 100 report "P is not 100" severity Note;
          assert P = 200 report "P is not 200" severity Note;
        end A;
        ------------------------------------------------------
        entity Top is
        end Top;

        architecture Structure of Top is
          component C
            port (PC: buffer integer := 200);
          end component;
        begin
          instance: C port map (OPEN);
        end Structure;

        configuration First of Top is
          for Structure
            for instance: C
              use entity Work.E(A) port map (PC);
            end for;
          end for;
        end First;

Which assertion statement statement fails?  The answer to this question hinges
on which of P or PC does not have a source.  The LRM is a bit confused on this
point.  The applicable LRM passages are the second sentence of paragraph 7 and
the first sentence of paragraph 8 of Section 4.3.1.2 (on page 4-6):

        For a signal of a scalar type, each source is either a driver
        (see Section 9.2.1) or an out, inout, buffer, or linkage port
        *of a component instance* with which the signal is associated.
        [Emphasis mine.]

        If a subelement of a resolved signal of composite type is
        associated as an actual in a port map clause *(either in a
        component instantiation statement or in a binding indication)*,
        and the corresponding formal is of mode out, inout, buffer, or
        linkage, then every scalar subelement of that signal must be
        associated exactly once with such a formal in the same port map
        clause, and the collection of the corresponding formal parts
        taken together constitute one source of the signal.  [Again, the
        emphasis is mine.]

Even though paragraph 8 doesn't apply to the above code (the port is a scalar),
its construction is somewhat in parallel to paragraph 7, except for the wording
"... in a component instance ..." in paragraph 7 and "... in a component
instantiation statement ..." in paragraph 8, where they seem to be anti-
parallel.  This anti-parallelism is probably inadvertent, and in fact, probably
incorrect.  This position can be motivated by looking at the equivalent block
model for the above design hierarchy:

        Top:
          block
          begin
            Structure:
              block
              begin
                instance:
                  block
                    port (PC: buffer integer := 200);
                    port map (OPEN);
                  begin
                    E:
                      block
                        port (P: buffer integer := 100);
                        port map (PC);
                      begin
                        A:
                          block
                          begin
                            process
                            begin
                              assert P = 100
                                report "P is not 100"
                                severity Note;
                              wait on P;
                            end process;
                            process
                            begin
                              assert P = 200
                                report "P is not 200"
                                severity Note;
                              wait on P;
                            end process;
                          end block A;
                      end block E;
                  end block instance;
              end block Structure;
          end block Top;

Paragraph 7 appears to state that PC has no sources, where if paragraph 8 was
operative, P would seem to have no sources.  Which is the correct situation?



Proposed Resolution
-------------------
By inspection of the equivalent block hierarchy, it seems reasonable to
conclude that PC has no sources and that P has a source (which is PC).  This
situation should be true no matter if the type(s) of these ports were scalar or
composite.

The LRM should be repaired to effect this conclusion.


VASG-ISAC Analysis & Rationale
------------------------------
TBD


VASG-ISAC Recommendation for IEEE Std 1076-1987
-----------------------------------------------
TBD


VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
TBD