VHDL Issue Number:      0168
Classification:         Language Definition Problem
Language Version:       VHDL-87
Summary:                The index bounds of certain concatenations are illegal.
Related Issues:         None.
Relevant LRM Sections:  7.2.3
Key Words and Phrases:  Concatenation, index bounds
Current Status:         Submitted
1076-1993 Disposition:  Closed (All Issues Completely Addressed)
Disposition Rationale:  Section 7.2.4 was revised.
Superseded By:          N/A
-----------------------
Date Submitted:         1991/03/14
Author of Submission:   Paul Menchini
Author's Affiliation:   CAD Language Systems, Inc.
Author's Post Address:  P.O. Box 13036
                        Research Triangle Park, NC  27709-3036
Author's Phone Number:  (919) 361-1913
Author's Fax Number:    
Author's Net Address:   mench@clsi.com
-----------------------
Date Analyzed:          TBD
Author of Analysis:     TBD
Revision Number:        $Revision: 1.9 $
Date Last Revised:      $Date: 1995/08/04 01:43:10 $


Description of Problem
----------------------
Consider the following VHDL fragment:

        variable a, b: Bit_Vector (7 downto 0);
            :
        b := a (6 downto 3) & a (5 downto 2);

What are the bounds of the result computed by the concatenation?

According to item 1 of paragraph 2 of Section 7.2.3:

        The left bound of this result is the left bound of the left
        operand....  The direction of the result is the direction of the
        left operand....

What is not stated (but is easily assumed) is how to compute the right bound.

Applying these rules, the index range for the result in the example is 6 downto
-1, which is not a valid range for Bit_Vector.


Proposed Resolution
-------------------
Since the number of elements is correct, an implicit subtype conversion takes
place across the assignment, so this is only a definitional difficulty.  One
way out would be to state that the bounds computation takes place either in the
base type of the index subtype (in which case the bounds computations would
take place in Integer) or that the bounds computation takes place in
*universal_integer*.

For completeness, the computation of the right bound of the result of
concatenation should be specified.


VASG-ISAC Analysis & Rationale
------------------------------
TBD


VASG-ISAC Recommendation for IEEE Std 1076-1987
-----------------------------------------------
TBD


VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
TBD