VHDL Issue Number:      0174
Classification:         Language Definition Problem
Language Version:       VHDL-87
Summary:                A restriction is needed on T'Val's parameter.
Related Issues:         None.
Relevant LRM Sections:  14.1
Key Words and Phrases:  'Val, predefined attribute
Current Status:         Submitted
1076-1993 Disposition:  Closed (All Issues Completely Addressed)
Disposition Rationale:  Section 14.1 was revised.
Superseded By:          N/A
-----------------------
Date Submitted:         1991/03/15
Author of Submission:   Paul Menchini
Author's Affiliation:   CAD Language Systems, Inc.
Author's Post Address:  P.O. Box 13036
                        Research Triangle Park, NC  27709-3036
Author's Phone Number:  (919) 361-1913
Author's Fax Number:    
Author's Net Address:   mench@clsi.com
-----------------------
Date Analyzed:          TBD
Author of Analysis:     TBD
Revision Number:        $Revision: 1.9 $
Date Last Revised:      $Date: 1995/08/04 01:45:13 $


Description of Problem
----------------------
The expression "T'Val (T'Pos (T'High) + 1)" doesn't make any sense, yet is not
disallowed by the LRM.


Proposed Resolution
-------------------
Add the restriction to the definition of T'Val (X) that an error occurs unless
T'Pos (T'Low) <= X <= T'Pos (T'High).


VASG-ISAC Analysis & Rationale
------------------------------
TBD


VASG-ISAC Recommendation for IEEE Std 1076-1987
-----------------------------------------------
TBD


VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
TBD