VHDL Issue Number: 0178 Classification: Language Definition Problem Language Version: VHDL-87 Summary: VPI Issue 2 -- Specifications applying to 0 entities Related Issues: 0191 (supersedes it) Relevant LRM Sections: 5.1, 5.2, 5.3 Key Words and Phrases: TBD Current Status: ISAC Approved 1076-1993 Disposition: Superseded (ISAC Issues Outstanding) Disposition Rationale: N/A Superseded By: 1023 ----------------------- Date Submitted: 1991/03/15 Author of Submission: J. R. Armstrong Author's Affiliation: Virginia Polytechnic Institute and State University Author's Post Address: Bradley Department of Electrical Engineering Virginia Polytechnic Institute and State University Blacksburg, VA 24061 Author's Phone Number: (703) 231-4723 Author's Fax Number: Author's Net Address: JRA@VTVM1.CC.VT.EDU ----------------------- Date Analyzed: 1991/12/03 Author of Analysis: Clive Charlwood Revision Number: $Revision: 1.11 $ Date Last Revised: $Date: 1995/05/13 21:53:48 $ Description of Problem ---------------------- The LRM states that "a specification always relates to entities that already exist." This does not say that it is an error if a specification is present and no entities of that class exist. In addition, can "all" be used if no cor- responding entity class is declared? Test Files: ch05/02010101.vhd (see issue 10 and 16 also), ch01/s02/S1/01030101.vhd (see comment sec- tion), ch05/s01/05010102.vhd Comment: Intent of the VHDL standard is not clear here. -- ##50002111441FF************************************************************ --+ File: [SUITE.CH05]02010101.VHD -- --+ Copyright: (c) 1987, 1988 by CAD Language Systems, Inc. All rights reserve -- --+ LRM_version: IEEE Std. 1076-1987 -- --+ Subsets: -- --+ Description: -- --+ Test_point - (050000_020101) " A specification always relates to entities -- that already exist." -- --+ Test_objective (1)- Test that specification( attribute, configuration -- and disconnection specifications) always relate to entities that already -- exist." -- This test should indicate an error because the last attribute specificatio -- relates to the entity class constant which does not exist. -- --+ References : None -- --+ Instructions: None -- --+ Keywords: specifications, attribute specification -- --+ Test_Results: Expect_Failure . Output_checked. Approximate Error Message: -- " The attribute specification does not relate to an existing entity." -- --+ Test_type: Locally Static Semantic -- --+ History: Created /CLSI 08-30-88 --+ Modified RA/Vtech 04-15-89 -- Corrected CHC/Vtech 12-20-89 -- Modified CHC/Vtech 5-4-90 -- --+ Comments: CLSI-FILE : [000000.SPECS.ATTR]23 -- -- This test will be sent to VASG for the following two reasons: -- 1) Zycad claimed that 'a' is a subtype and thus the entity class -- of the attribute specification 'left' should be 'subtype', -- not 'type'. -- 2) There is no constant declaration. Can the entity class -- 'constant' be used for the attribute specification? --**************************************************************************** package p23 is type a is range 1 to 10; attribute left: integer; attribute left of a : type is 5; -- (Refer to the Comment section) attribute left of all : constant is 5; -- Failure_here -- (Refer to the Comment section) end; --##12101311245FF************************************************************* -- --+ File: [SUITE.CH01.S02.S1]01030101.VHD -- --+ Copyright: (c) 1986 by Intermetrics. All rights reserved -- --+ LRM_Version: IEEE Std. 1076-1987 -- --+ Subsets: None -- --+ Description: -- --+ Test_point - (010210_010301) The block declarative part, if -- not empty, must consist of the given block declarative items. -- --+ Test_objective (1) - Test if the given block declarative -- items are valid. -- --+ References: None -- --+ Instructions: None -- --+ Keywords: Block declarative items -- --+ Test_Results: Expect_Success. Output_Checked. --- --+ Test_Type: Locally Static Semantic -- --+ History: Modified MM/MCC 6-9-89 -- Modified CHC/VT 8-23-89 -- Corrected CHC/VT 12-19-89 -- --+ Comments: Original filename s-01-2-1-0001a.vhd -- Corrected end of BEHAVIOR - jsgrout 31aug88 -- -- This file originally had a disconnection specification: -- disconnect all: BIT after 0 ns; -- The reason for deleting this statement was that the -- disconnection_specification needs a guarded_signal_specification -- and this test doesn't have any guarded signals. MCC objects -- on the grounds that this issue has to be resolved by the VASG. -- *************************************************************************** package P is type BIT is ('0', '1'); end P; entity E is port (A : BIT; B : out BIT; C, D : Boolean) ; end E; architecture AA of E is procedure P1 is begin return; end P1; function F1 return BIT is begin return '0'; end F1; type Q is range 10.5 to 11.5; subtype R is REAL; constant C1 : REAL := 1.39; signal S : BIT; component E2 port (A : in BIT); end component; for TEST : E2 use open ; use WORK.P.all; begin TEST : E2 port map ( S ); end AA; --##51005112445FF************************************************************* -- --+ File: [SUITE.CH05.S01]05010102.VHD -- --+ Copyright: (c) 1986 by Intermetrics Inc. All rights reserved -- --+ LRM_Version: IEEE Std. 1076-1987 -- --+ Subsets: None -- --+ Description: -- --+ Test_point - (050100_050101) "An attribute specification for an at- -- tribute of a design unit (i.e., an entity, an architecture, -- a configuration, or a package) must appear immediately -- within the declarative part of that design unit." -- --+ Test_objective (2) - Test if an attribute specification for a body must -- appear only immediately within the declarative -- part of a body declaration. -- --+ References: None -- --+ Instructions: None -- --+ Keywords: Attribute specification, Design Unit -- --+ Test_Results: Expect_Failure. Output_Checked. Approximate -- Error Message: "Entity attribute specification permitted only in entity -- declarative part." -- --+ Test_Type: Locally Static Semantic -- --+ History: Created MM/MCC 6-29-89 -- Modified CHC/VT 8-21-89 -- Modified CHC/VT 5-8-90 -- --+ Comments: Original file name: E-05-1-1-0013A.VHD -- Updated to 1076-1987 VHDL, checked w/Recognizer. -- (Deene)ogden@mcc.com 20jun88 -- Corrected USE stmts. Fri Sep 30 12:36:57 1988 Steve Grout -- -- Zycad claimed that 'all' can be used in an attribute specificati -- even if no corresponding entity class is declared. -- This will be sent to VASG for clarification. --**************************************************************************** -- Begin test: >>> package P is attribute A1 : CHARACTER; end P; package body P is function F1 return BOOLEAN is attribute A1 of all : entity is '5'; -- Failure_here -- ERROR : entity attribute specification permitted only in entity -- declarative part begin return FALSE; end F1 ; end P ; Proposed Resolution ------------------- TBD VASG-ISAC Analysis & Rationale ------------------------------ *** This IR supersedes IR 0191 (the same issue for configuration specifications). The last two bullets in LRM 5.1 page 5-2 state: - If the reserved word *others* is supplied, then the attribute specification applies to entities of the specified class that are declared in the immediately enclosing declarative region, provided that each such entity is not explicitly named in the entity name list of a previous attribute specification. - If the reserved word *all* is supplied, then the attribute specification applies to all entities of the specified class that are declared in the immediately enclosing declarative region. These paragraphs do not explicitly state whether or not the "others" or "all" may apply to "zero or more" or "one or more" entities. Therefore the LRM needs to be clarified to explicitly state whether or not it is legal to attribute zero entities. The ISAC feels that it is quite possible to envisage a situation where a designer may want to attribute 0 entities. For Example, she may want to attribute all of the signals declared within a given block with information (perhaps some kind of derating information). She would then create boiler-plate code as follows: b: Block ... signal declarations (if any) ... attribute derate of all: signal is 1; begin end block; If it were not legal to attribute 0 signals then the attribute specification above would have to be omitted from blocks that did not contain signals declarations. This would be a little cumbersome. Therefore, it is our belief that it should be legal to attribute zero or more entities. VASG-ISAC Recommendation for IEEE Std 1076-1987 ----------------------------------------------- Interpret the above paragraphs (and the corresponding paragraphs in 5.2, and 5.3) to allow an attribute specification to zero or more entities. VASG-ISAC Recommendation for Future Revisions --------------------------------------------- Rework the above paragraphs as follows (changes enclosed in **'s for emphasis). - If the reserved word others is supplied, then the attribute specification applies to **each entity, if any,** of the specified class that are declared in the immediately enclosing declarative region, provided that **the** entity is not explicitly named in the entity name list of a previous attribute specification. - If the reserved word all is supplied, then the attribute specification applies to **each entity, if any,** of the specified class that is declared in the immediately enclosing declarative region. Note: For the reasons listed above, and to be consistent. The last two bullets in 5.3 (Disconnect Specification) and 5.2 (Configuration Specification). Should also be corrected as above.