VHDL Issue Number:      0181
Classification:         Language Definition Problem
Language Version:       VHDL-87
Summary:                VPI Issue 5 -- Unassociated formal ports
Related Issues:         TBD
Relevant LRM Sections:  1.1.1.2, 4.3.2.1
Key Words and Phrases:  TBD
Current Status:         Closed (Andy Tsay)
1076-1993 Disposition:  Closed (All Issues Completely Addressed)
Disposition Rationale:  LRM clearly states that formal ports may be unassociated
                        under certain circumstances.
Superseded By:          N/A
-----------------------
Date Submitted:         1991/03/15
Author of Submission:   J. R. Armstrong
Author's Affiliation:   Virginia Polytechnic Institute and State University
Author's Post Address:  Bradley Department of Electrical Engineering
                        Virginia Polytechnic Institute and State University
                        Blacksburg, VA 24061
Author's Phone Number:  (703) 231-4723
Author's Fax Number:    
Author's Net Address:   JRA@VTVM1.CC.VT.EDU
-----------------------
Date Analyzed:          1994/07/27
Author of Analysis:     Andy Tsay (Fintronic USA, tsay@fintronic.com)
Revision Number:        $Revision: 1.8 $
Date Last Revised:      $Date: 1995/08/04 01:45:13 $


Description of Problem
----------------------
  Do all formal ports have to be associated?

  Test File: ch05/s02/s2/02020101.vhd (see comment section)

  Comment : VASG issue #66 addresses the problems of unassoci-
  ated formal ports.


  --##52202211145FF5212512******************************************************
  --
  --+ File: [SUITE.CH05.S02.S2]02020101.VHD
  --
  --+ Copyright: (c) 1986 by Intermetrics Inc. All rights reserved
  --
  --+ LRM_Version: IEEE Std. 1076-1987
  --
  --+ Subsets: None
  --
  --+ Description:
  --
  --+ Test_point -   (050220_020201) "if an entity declaration is visible but ha
  --                  no associated architecture body, then the default entity
  --                  aspect is of the form
  --                      entity entity_name
  --                  where the entity name is the simple name of the instantiat
  --                  component."
  --
  --+ Test_objective (1) - Test that no error occurs when only the reserved
  --                  word entity and an entity name are used as an entity
  --                  aspect for an entity which has no associated architecture
  --                  body.
  --
  --+ References: Secondary LRM Coverage: 050212_050102
  --
  --+ Instructions: None
  --
  --+ Keywords: Instantiation Labels, Component Specification
  --
  --+ Test_Results: Expect_Success. Self_Checked.
  --
  --+ Test_Type: Locally Static Semantic
  --
  --+ History: Created MM/MCC 7-05-89
  --           Modified CHC/VT 8-22-89
  --           Corrected CHC/VT 12-20-89
  --
  --+ Comments: Original file name: S-05-1-2-1301A.VHD
  --          15-September-1988 13:50:00 by David Franke(Franke@mcc.com)
  --       Added package name to entity name in configuration specification
  --          Updated to 1076-1987 VHDL, checked w/Recognizer.
                                           (Deene)ogden@mcc.com 20jun88
  --
  --          The original test had the following additional port declarations:
  --            (in the entity EMP)
  --                A : Integer := 1 ;
  --                C : in Boolean := true;
  --            Since the issue raised by MCC (VASG #66, the problem of
  --            unassociated formal ports) is not relevant to this test
  --            point or test objective, the recommendations in VASG #66
  --            are not considered here.
  --
  --****************************************************************************

   entity EMP  is
       port (B : in Bit );
   end EMP ;

  entity EMT  is
      port (sig     : bit) ;
  end EMT;

  architecture ABC of EMT is
  begin
   BB : block
     component LA port ( S1 : Bit );
     end component;
     for all : LA
       use
        entity work.EMP
        port map (B => S1)
      ;
    begin
     CIS1 : LA port map (S1 => sig);
    end block BB;

    process
        begin
       assert FALSE
       report "TEST OK for given Test Point"
       severity note;
       wait;
    end process;
  end ABC ;


Proposed Resolution
-------------------
TBD


VASG-ISAC Analysis & Rationale
------------------------------
The LRM'87 clearly states that formal ports may be unassociated under
certain circumstances.
Issue closed.


VASG-ISAC Recommendation for IEEE Std 1076-1987
-----------------------------------------------
TBD


VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
TBD