VHDL Issue Number:      0185
Classification:         Language Definition Problem
Language Version:       VHDL-87
Summary:                VPI Issue 9 -- Range constraints in alias decls
Related Issues:         0026
Relevant LRM Sections:  4.3.4
Key Words and Phrases:  subtype indication, scalar alias declaration 
Current Status:         Superseded
1076-1993 Disposition:  Closed (All Issues Completely Addressed)
Disposition Rationale:  Already superseded
Superseded By:          N/A
-----------------------
Date Submitted:         1991/03/15
Author of Submission:   J. R. Armstrong
Author's Affiliation:   Virginia Polytechnic Institute and State University
Author's Post Address:  Bradley Department of Electrical Engineering
                        Virginia Polytechnic Institute and State University
                        Blacksburg, VA 24061
Author's Phone Number:  (703) 231-4723
Author's Fax Number:    
Author's Net Address:   JRA@VTVM1.CC.VT.EDU
-----------------------
Date Analyzed:          1992/01/02
Author of Analysis:     Alex Zamfirescu 
Revision Number:        $Revision: 1.8 $
Date Last Revised:      $Date: 1995/05/13 19:34:42 $


Description of Problem
----------------------
  Are range constraints in alias declarations al-
  lowed?

  Test File: ch04/s03/s4/03040101.vhd

  Comment: Range constraints in alias declarations  appear  to
  be legal as long as the matching element rule holds.


 
--##43403411245FF*************************************************************
 --
  --+ File: [SUITE.CH04.S03.S4]03040101.VHD
  --
  --+ Copyright: (c) 1986 by Intermetrics Inc. All rights reserved
  --
  --+ LRM_Version: IEEE Std. 1076-1987
  --
  --+ Subsets: None
  --
  --+ Description:
  --
  --+ Test_point -     (040340_030401) "[When the object denoted by the name is
  --        referenced via the alias defined by the  alias  declara-
  --        tion,  it  is viewed as if it were of the subtype speci-
  --        fied by the subtype indication.]
  --              If this subtype is a one-dimensional
  --              array subtype, the subtype must include a matching ele-
  --              ment for each element of that object denoted by the name."
  --
  --+ Test_objective (1) - Test that the subtype indication in an alias
  --  declaration may specify a different direction from that specified in the
  --  declaration of the   object it denotes
  --
  --+ References: None
  --
  --+ Instructions: None
  --
  --+ Keywords:  Alias declaration, Subtype, One-dimensional Array,
  --             Matching Element
  --
  --+ Test_Results: Expect_Success. Output_Checked.
  --
  --+ Test_Type: Locally Static Semantic
  --
  --+ History: Created MM/MCC 6-27-89
  --           Modified CHC/VT 8-25-89
  --           Modified CHC/VT 5-4-90
  --
  --+ Comments: Original file name: S-04-2-1-4003A.VHD
  --            Updated to 1076-1987 VHDL, checked w/Recognizer.
  --                                            (Deene)Ogden@mcc.com 20jun88
  --            The use of range constraints is not clearly explained in
  --            LRM.  This will be sent to VASG for clarification.
 
--****************************************************************************
 -- Begin test: >>>

  package Three_a is
       type meters is (one_hr, two_hr, nine_hr);

          function N return boolean;
  end Three_a;

  package body Three_a is
          function N return boolean is
           variable early_choice : meters range nine_hr downto one_hr;
            -- Object has descending direction.
           alias late_choice : meters range one_hr to nine_hr is early_choice;
            -- Alias has ascending direction.
              begin
            return True;
       end N;
  end Three_a;


Proposed Resolution
-------------------
Ignore constraint implied by the subtype indication in a scalar
alias declaration. Late_choice and early_choice above have both
descending direction.


VASG-ISAC Analysis & Rationale
------------------------------  
VASG-ISAC Recommendation for IEEE Std 1076-1987 for the ISAC-Approved
VHDL Issue Number 0026 solves the problem raised by this IR. 

       The constraint implied by the subtype indication in 
       a scalar alias declaration is ignored.

Test is correct VHDL code, and will check what it claims.


VASG-ISAC Recommendation for IEEE Std 1076-1987
-----------------------------------------------
Refer to IR-0026. The present IR is now superseded by IR-0026. 


VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
See issue report 0026, lcs_0008.1 and lcs_0038.1.
Test might become invalid in the future, as language might change 
(be clarified) without upward compatibility in this area.