VHDL Issue Number:      0189
Classification:         Language Definition Problem
Language Version:       VHDL-87
Summary:                VPI Issue 13 -- Integer subtypes & operations
Related Issues:         Superseded By IR 1036 (Andy Tsay)
Relevant LRM Sections:  3.1.2, 3.1.4, 7.2.4, 7.2.6, 7.3.5, 8.8
Key Words and Phrases:  Integer Type Definition, Subtype, Range Constraints
Current Status:         Submitted
1076-1993 Disposition:  Superseded (ISAC Issues Outstanding)
Disposition Rationale:  N/A
Superseded By:          1036
-----------------------
Date Submitted:         1991/03/15
Author of Submission:   J. R. Armstrong
Author's Affiliation:   Virginia Polytechnic Institute and State University
Author's Post Address:  Bradley Department of Electrical Engineering
                        Virginia Polytechnic Institute and State University
                        Blacksburg, VA 24061
Author's Phone Number:  (703) 231-4723
Author's Fax Number:    
Author's Net Address:   JRA@VTVM1.CC.VT.EDU
-----------------------
Date Analyzed:          TBD
Author of Analysis:     TBD
Revision Number:        $Revision: 1.10 $
Date Last Revised:      $Date: 1995/08/04 01:45:13 $


Description of Problem
----------------------
  What is the result type of an expression in which
  arithmetic operations are performed on an  integer  subtype?
  Should  the  result  be  in  the integer subtype range to be
  valid?

  Test File: ch08/s07/06010102.vhd (see comment section)


  --##87006112145FF*************************************************************
  --
  --+ File: [SUITE.CH08.S07]06010102.VHD
  --
  --+ Copyright: (c) 1986 by Intermetrics Inc. All rights reserved
  --
  --+ LRM_Version: IEEE Std. 1076-1987
  --
  --+ Subsets: None
  --
  --+ Description:
  --
  --+ Test_point -    (080700_060101)  "The  simple  expression  and  discrete
  --             ranges given as choices in a case statement must be  lo-
  --             cally static."
  --
  --+ Test_objective (2) - Test that  the case expression may be a complex
  --                     static expression.
  --
  --+ References: None
  --
  --+ Instructions: None
  --
  --+ Keywords:   Case statement
  --
  --+ Test_Results: Expect_Success. Self_Checking.
  --
  --+ Test_Type: Locally Static Semantic
  --
  --+ History: Created MM/MCC 7-26-89
  --           Corrected KSC/VT 12-22-89
  --           Modified CHC/VT  5-4-90
  --
  --+ Comments:    Original file name: S-08-1-8-0002A.VHD
  --               12-September-1988 00:42:38 by David Franke(Franke@mcc.com)
  --         Replaced return with null in process
  --               Updated to 1076-1987 VHDL, checked w/Recognizer.
  --                                          (Steve)Grout@mcc.com 20jun88
  --
  --               Zycad claimed that 'others' must be included in the
  --               case statement because the case expression is
  --               type of INTEGER.
  --               This will be sent to VASG for clarification.
  --****************************************************************************

  package P is
    function F return BOOLEAN;
  end P;

  package body P is
     function F return BOOLEAN is
       type I1 is range 0 to 10;
       variable V1 : I1 := 7;
     begin
       case V1 * 2 /4 is
         when 0 to 5 => return TRUE;
         when 6 to 10 => return FALSE;
       end case;
      end F;
  end P;

  package P1 is
     function F return REAL;
  end P1;

  package body P1 is
     function F return REAL is
      subtype ST is INTEGER range 5 downto -2;
      variable V1 : ST;
     begin
        case ST'(V1 - 3) is
       when 4 downto -1 => return 0.1;
       when -2 | 5 => return 9.0;
        end case;
      end F;
  end P1;

  entity E  is
      port (PT: inout REAL) ;
  end E;

  architecture BB of E is
   begin
    process
      subtype ST is INTEGER range 20 to 45;
      variable V1 : ST := 20;
    begin
      case V1>=20 and V1<30 is
          when TRUE => -- return;
            null;
          when FALSE => -- return;
            null;
      end case;

          assert FALSE
       report "TEST OK for given Test Point"
       severity note;
       wait;
    end process;
  end BB;

  architecture AB of E is
   begin
    process
      type T1 is (U,V,W,X,Y,Z);
      variable V1 : T1 := Z;
    begin
      case V1<W or V1>X or V1=U is
          when TRUE => PT <= 0.9;
          when FALSE => PT <= 1.1;
      end case;

          assert FALSE
       report "TEST OK for given Test Point"
       severity note;
       wait;
    end process;
  end AB;


Proposed Resolution
-------------------
TBD


VASG-ISAC Analysis & Rationale
------------------------------
TBD


VASG-ISAC Recommendation for IEEE Std 1076-1987
-----------------------------------------------
TBD


VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
TBD