VHDL Issue Number: 0195 Classification: Language Definition Problem Language Version: VHDL-87 Summary: VPI Issue 19 -- Referencing ports with expanded names Related Issues: 0113 Relevant LRM Sections: 6.3 Key Words and Phrases: port, expanded name, name. Current Status: Superseded 1076-1993 Disposition: Closed Disposition Rationale: Superseded by 0113 Superseded By: 0113 ----------------------- Date Submitted: 1991/03/15 Author of Submission: J. R. Armstrong Author's Affiliation: Virginia Polytechnic Institute and State University Author's Post Address: Bradley Department of Electrical Engineering Virginia Polytechnic Institute and State University Blacksburg, VA 24061 Author's Phone Number: (703) 231-4723 Author's Fax Number: Author's Net Address: JRA@VTVM1.CC.VT.EDU ----------------------- Date Analyzed: 1991/11/21 Author of Analysis: Oz Levia Revision Number: $Revision: 1.11 $ Date Last Revised: $Date: 1995/07/26 22:22:18 $ Description of Problem ---------------------- Can a port defined in an entity be used as the suffix of an expanded name whose prefix is the name of an architecture body associated with the entity? Test File: ch06/s03/08010104.vhd LRM section 6.3, paragraph 8 specifies that: An expanded name denotes an entity declared immediately within a named construct if the prefix denotes a construct that is an entity, an architecture, a subprogram, a block statement, a process statement, or a loop statement, and the suffix is the simple name, character literal, or operator symbol of an entity whose declaration occurs immediately within that construct. THIS FORM OF EXPANDED NAME IS ONLY ALLOWED WITHIN THE CONSTRUCT ITSELF. Thus, in the test, the expanded name a7.p is considered to be illegal because the port p is not declared immediately within the architecture body a7. However, a7.p could also be considered to be legal considering that p is declared within the entity e7 and that the entity e7 and the corre- sponding architecture a7 together form one declarative re- gion. --##63008114441FF***********************************************************- ** --+ File: [SUITE.CH06.S03]08010104.VHD -- --+ Copyright: (c) 1987, 1988 by CAD Language Systems, Inc. All rights reserve -- --+ LRM_version: IEEE Std. 1076-1987 -- --+ Subsets: -- --+ Description: -- --+ Test_point - (060300_080101) "An expanded name denotes an entity declared -- immediately within a named construct if the prefix denotes a construct -- that is an entity, an architecture, a subprogram, a block statement, or a -- loop statement, and the suffix is the simple name, character literal, or -- operator symbol of an entity whose declaration occurs immediately within -- that construct." -- --+ Test_objective (4)- Test if the suffix of the expanded name is declared -- immediately within the construct denoted by the prefix of the expanded -- name. -- --+ References: None -- --+ Instructions: None -- --+ Keywords: Expanded Name, Named Construct -- --+ Test_Results: Expect_Failure. Output_Checked. Approximate error message: -- "Declaration of suffix must occur within the construct denoted by the -- prefix". -- --+ Test_type: Locally Static Semantic -- --+ History: Created /CLSI 08-30-88 -- -- Modified: KSC/VTech 05-22-89 -- --+ Comments: CLSI FILE: [000000.NAMES.SELECTED]07 -- --**************************************************************************- ** entity e7 is port (p: in bit); end e7; architecture a7 of e7 is signal q: bit; begin process (a7.p, a7.q) begin end process; end; Proposed Resolution ------------------- TBD VASG-ISAC Analysis & Rationale ------------------------------ This issue is similar to IR 0113, which is resolved. VASG-ISAC Recommendation for IEEE Std 1076-1987 ----------------------------------------------- See "VASG-ISAC Analysis & Rationale" VASG-ISAC Recommendation for Future Revisions --------------------------------------------- No change is required or recommended.