VHDL Issue Number: 0199 Classification: Language Definition Problem Language Version: VHDL-87 Summary: The simulation cycle terminates too early. Related Issues: None. Relevant LRM Sections: 12.6.3 Key Words and Phrases: Simulation cycle, termination, Time'High Current Status: Submitted 1076-1993 Disposition: Closed (All Issues Completely Addressed) Disposition Rationale: LRM was revised. Superseded By: N/A ----------------------- Date Submitted: 1991/03/16 Author of Submission: Paul Menchini Author's Affiliation: CAD Language Systems, Inc. Author's Post Address: P.O. Box 13036 Research Triangle Park, NC 27709-3036 Author's Phone Number: (919) 361-1913 Author's Fax Number: Author's Net Address: mench@clsi.com ----------------------- Date Analyzed: TBD Author of Analysis: TBD Revision Number: $Revision: 1.9 $ Date Last Revised: $Date: 1995/08/04 01:45:13 $ Description of Problem ---------------------- Step 1 of the simulation cycle (from Section 12.6.3 on page 12-14) states (in part): Simulation is complete when time advances to TIME'High. Consider the following process in light of this quote: process begin wait for Time'High; loop : S <= after 0 nS; wait for 0 nS; : exit when ; : end loop; wait; end process; It seems that the loop in this process never executes! Proposed Resolution ------------------- Modify the quoted sentence to read: Simulation is complete when simulation time equals TIME'High and no driver is active and no process has resumed. VASG-ISAC Analysis & Rationale ------------------------------ TBD VASG-ISAC Recommendation for IEEE Std 1076-1987 ----------------------------------------------- TBD VASG-ISAC Recommendation for Future Revisions --------------------------------------------- TBD