VHDL Issue Number:      0201
Classification:         Language Deficiencies and Modeling Problems
Language Version:       VHDL-87
Summary:                Add an optional condition to return statements.
Related Issues:         None.
Relevant LRM Sections:  8.11
Key Words and Phrases:  Return statements, conditions
Current Status:         Submitted
1076-1993 Disposition:  Bugs Fixed, Enhancements Outstanding (No ISAC Issues)
Disposition Rationale:  Non-ISAC issues outstanding.
Superseded By:          N/A
-----------------------
Date Submitted:         1991/03/16
Author of Submission:   Paul Menchini
Author's Affiliation:   CAD Language Systems, Inc.
Author's Post Address:  P.O. Box 13036
                        Research Triangle Park, NC  27709-3036
Author's Phone Number:  (919) 361-1913
Author's Fax Number:    
Author's Net Address:   mench@clsi.com
-----------------------
Date Analyzed:          TBD
Author of Analysis:     TBD
Revision Number:        $Revision: 1.9 $
Date Last Revised:      $Date: 1995/08/04 01:45:13 $


Description of Problem
----------------------
Return statements would benefit from a condition clause.  Currently, such
conditional returns from subprograms must be expressed as:

        if <condition> then
          return [<expression>];
        end if;

A more concise way, and one that is analogous to exit and next statements is:

        return [<expression>] when <condition>;


Proposed Resolution
-------------------
Add an optional condition clause to return statements.  The suggested syntax
is:

        return_statement ::=
                RETURN [ expression] [ WHEN condition ];


VASG-ISAC Analysis & Rationale
------------------------------
TBD


VASG-ISAC Recommendation for IEEE Std 1076-1987
-----------------------------------------------
TBD


VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
TBD