VHDL Issue Number: 0205 Classification: Language Definition Problem Language Version: VHDL-87 Summary: May slices of formals be independently associated? Related Issues: None. Relevant LRM Sections: 4.3.3.2 Key Words and Phrases: Independent formal subelement association, slices Current Status: Submitted 1076-1993 Disposition: Closed (All Issues Completely Addressed) Disposition Rationale: Section 4.3... was revised Superseded By: N/A ----------------------- Date Submitted: 1991/03/18 Author of Submission: Paul Menchini Author's Affiliation: CAD Language Systems, Inc. Author's Post Address: P.O. Box 13036 Research Triangle Park, NC 27709-3036 Author's Phone Number: (919) 361-1913 Author's Fax Number: Author's Net Address: mench@clsi.com ----------------------- Date Analyzed: TBD Author of Analysis: TBD Revision Number: $Revision: 1.9 $ Date Last Revised: $Date: 1995/05/13 19:34:42 $ Description of Problem ---------------------- The first sentence of paragraph 11 of Section 4.3.3.2 (on page 4-12) states: A formal may either be an explicitly declared interface object or it may be a subelement of such an interface object. This statement allows the elements of a formal to be individually associated. Does it also either allow (or prohibit) a slice of a formal to be associated with a single association element? Proposed Resolution ------------------- There seem to be minimal additional difficulties imposed by allowing a slice of a formal to be associated with a single association element. Modify the quoted sentence to read: A formal may be either 1. an explicitly declared interface object, 2. a subelement of such an interface object, or 3. a slice of such an interface object or subelement thereof. VASG-ISAC Analysis & Rationale ------------------------------ TBD VASG-ISAC Recommendation for IEEE Std 1076-1987 ----------------------------------------------- TBD VASG-ISAC Recommendation for Future Revisions --------------------------------------------- TBD