VHDL Issue Number:      0211
Classification:         Language Definition Problem
Language Version:       VHDL-87
Summary:                The restriction that prohibits signal attributes from
                        having drivers is mislocated.
Related Issues:         None.
Relevant LRM Sections:  4.4, 4.3.3, 6.6, 14.1
Key Words and Phrases:  Signal attributes, 'Delayed, 'Stable, 'Quiet,
                        'Transaction
Current Status:         Submitted
1076-1993 Disposition:  Bugs Fixed, Enhancements Outstanding (No ISAC Issues)
Disposition Rationale:  Non-ISAC issues outstanding.
Superseded By:          N/A
-----------------------
Date Submitted:         1991/03/18
Author of Submission:   Paul Menchini
Author's Affiliation:   CAD Language Systems, Inc.
Author's Post Address:  P.O. Box 13036
                        Research Triangle Park, NC  27709-3036
Author's Phone Number:  (919) 361-1913
Author's Fax Number:    
Author's Net Address:   mench@clsi.com
-----------------------
Date Analyzed:          TBD
Author of Analysis:     TBD
Revision Number:        $Revision: 1.9 $
Date Last Revised:      $Date: 1995/08/04 01:45:13 $


Description of Problem
----------------------
The last sentence of paragraph 1 of Section 4.4 states "Predefined attributes
that are signals may not be updated."  Since this section deals with attribute
declarations, this is an obscure location in which to place this restriction.

A better place to put this restriction is in the individual attributes in
Section 14.1; alternatively, one of Sections 4.3.3 (when discussing object
updating), or 6.6 could contain this restriction.


Proposed Resolution
-------------------
TBD


VASG-ISAC Analysis & Rationale
------------------------------
TBD


VASG-ISAC Recommendation for IEEE Std 1076-1987
-----------------------------------------------
TBD


VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
TBD