VHDL Issue Number:      0212
Classification:         Language Deficiencies and Modeling Problems
Language Version:       VHDL-87
Summary:                Specifications are unnecessarily redundant.
Related Issues:         None.
Relevant LRM Sections:  5.1, 5.2, 5.3
Key Words and Phrases:  Attribute specification, configuration specification,
                        disconnection specification, entity class,
                        component name, type mark, redundancy
Current Status:         Submitted
1076-1993 Disposition:  Bugs Fixed, Enhancements Outstanding (No ISAC Issues)
Disposition Rationale:  
Superseded By:          N/A
-----------------------
Date Submitted:         1991/03/18
Author of Submission:   Paul Menchini for Daniel Barclay
Author's Affiliation:   CAD Language Systems, Inc.
Author's Post Address:  P.O. Box 13036
                        Research Triangle Park, NC  27709-3036
Author's Phone Number:  (919) 361-1913
Author's Fax Number:    
Author's Net Address:   mench@clsi.com
-----------------------
Date Analyzed:          TBD
Author of Analysis:     TBD
Revision Number:        $Revision: 1.9 $
Date Last Revised:      $Date: 1995/05/13 19:34:42 $


Description of Problem
----------------------
All three specifications contain redundant elements:

1.  The entity class of an attribute specification is redundant when the entity
    name list consists of one or more entity designators.

2.  The component name of a configuration specification is redundant when the
    instantiation list consists of one or more instantiation labels.

3.  The type mark of a disconnection specification is redundant when the
    guarded signal list consists of one or more signal names.

Such redundancy serves as a source of errors and contributes to the verbosity
of VHDL.


Proposed Resolution
-------------------
Eliminate the redundant elements.  One possible syntax for each specification
follows:

1.  For attribute specifications:

        attribute specification ::=
          ATTRIBUTE attribute_designator OF entity_specification IS expression;

        entity_specification ::=
            entity_designator { , entity_designator }
            | OTHERS : entity_class
            | ALL : entity_class

        entity_designator ::= simple_name | operator_symbol

        entity_class :== <unchanged>

2.  For configuration specifications:

        configuration_specification ::=
            FOR component_specification USE binding_indication;

        component_specification ::=
            *instantiation*_label { , *instantiation*_label }
            | OTHERS : *component*_name
            | ALL : *component*_name

3.  For disconnection specifications:

        disconnection_specification ::=
             DISCONNECT guarded_signal_specification AFTER *time*_expression;

        guarded_signal_specification ::=
            *signal*_name { , *signal*_name }
            | OTHERS : type_mark
            | ALL : type_mark

Alternatively, the syntax of these specifications could be changed to make the
redundant elements optional; a semantic restriction would require the redundant
elements only when OTHERS or ALL were used.  This alternative would preserve
the upward compatibility of 1987 specifications.


VASG-ISAC Analysis & Rationale
------------------------------
TBD


VASG-ISAC Recommendation for IEEE Std 1076-1987
-----------------------------------------------
TBD


VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
TBD