VHDL Issue Number:      0214
Classification:         Language Definition Problem
Language Version:       VHDL-87
Summary:                The simulation cycle does not properly account for
                        processes executing "wait for" statements.
Related Issues:         None.
Relevant LRM Sections:  12.6.3
Key Words and Phrases:  Simulation cycle, timed wait, processes
Current Status:         Submitted
1076-1993 Disposition:  Closed (All Issues Completely Addressed)
Disposition Rationale:  Section 12.6.4 was revised
Superseded By:          N/A
-----------------------
Date Submitted:         1991/03/20
Author of Submission:   Paul Menchini
Author's Affiliation:   CAD Language Systems, Inc.
Author's Post Address:  P.O. Box 13036
                        Research Triangle Park, NC  27709-3036
Author's Phone Number:  (919) 361-1913
Author's Fax Number:    
Author's Net Address:   mench@clsi.com
-----------------------
Date Analyzed:          TBD
Author of Analysis:     TBD
Revision Number:        $Revision: 1.9 $
Date Last Revised:      $Date: 1995/05/13 19:34:42 $


Description of Problem
----------------------
Step 1 of the simulation cycle (on page 12-14) treats the two circumstances
under which time advances (or does not) differently.  It contains the
introductory clause "If no driver is active," but says nothing about processes
that are ready to resume during the just-started delta cycle.  This asymmetry
may be confusing.


Proposed Resolution
-------------------
Change the first sentence of Step 1 to read:

        If no driver is active and no process is ready to resume, then
        simulation time advances to the next time at which a driver
        becomes active or a process resumes.

As further clarification, an additional step should be inserted between steps 1
and 2:

        Each process that is ready to resume does so.

Finally, explicit identification of the beginning of the cycle may provide
further clarification.  If so, a new initial step should be added:

        The next simulation cycle begins.


VASG-ISAC Analysis & Rationale
------------------------------
TBD


VASG-ISAC Recommendation for IEEE Std 1076-1987
-----------------------------------------------
TBD


VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
TBD