VHDL Issue Number:      0217
Classification:         Language Definition Problem
Language Version:       VHDL-87
Summary:                Does the elaboration of a process statement create a
                        process?
Related Issues:         None.
Relevant LRM Sections:  12.4.4
Key Words and Phrases:  Elaboration, process statement, equivalent processes
Current Status:         Submitted
1076-1993 Disposition:  Superseded (ISAC Issues Outstanding)
Disposition Rationale:  N/A
Superseded By:          1072
-----------------------
Date Submitted:         1991/03/20
Author of Submission:   Paul Menchini
Author's Affiliation:   CAD Language Systems, Inc.
Author's Post Address:  P.O. Box 13036
                        Research Triangle Park, NC  27709-3036
Author's Phone Number:  (919) 361-1913
Author's Fax Number:    
Author's Net Address:   mench@clsi.com
-----------------------
Date Analyzed:          TBD
Author of Analysis:     TBD
Revision Number:        $Revision: 1.9 $
Date Last Revised:      $Date: 1995/07/26 23:42:27 $


Description of Problem
----------------------
The LRM would be clearer if Section 12.4.4 (on page 12-8) stated that the
elaboration of a process statement (whether explicitly specified or created as
the equivalent of another concurrent statement) creates a process.


Proposed Resolution
-------------------
Add a new initial step to paragraph 2 of Section 12.4.4:

    1.  The process is created.


VASG-ISAC Analysis & Rationale
------------------------------
TBD


VASG-ISAC Recommendation for IEEE Std 1076-1987
-----------------------------------------------
TBD


VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
TBD