VHDL Issue Number: 0223 Classification: Language Clarification Language Version: VHDL-87 Summary: Allowable prefixes on an expanded name Related Issues: Superseded By IR 1057 (Andy Tsay) Relevant LRM Sections: 6.2 Key Words and Phrases: expanded names, entity, architecture Current Status: Submitted 1076-1993 Disposition: Superseded (ISAC Issues Outstanding) Disposition Rationale: Superseded By: 1057 ----------------------- Date Submitted: 1991/03/21 Author of Submission: Laurence Groves Author's Affiliation: Synopsys Inc. Author's Post Address: 1098 Alta Ave. Mountain View, CA 94043 Author's Phone Number: (415) 962-5426 Author's Fax Number: Author's Net Address: larry@Synopsys.COM ----------------------- Date Analyzed: TBD Author of Analysis: TBD Revision Number: $Revision: 1.10 $ Date Last Revised: $Date: 1995/05/13 19:34:42 $ Description of Problem ---------------------- Consider the following: entity E is constant P : INTEGER := 1; end; architecture A of E is signal S : INTEGER; begin s <= E.P + A.P; end; In the above code fragment, the expanded names E.P and A.P denote the same object. LRM 6.3 paragraph 8 states: An expanded name denotes an entity declared immediately within a named construct if the prefix denotes a construct that is an entity, an architecture, [...] So entity and architectures are both allowed as prefixes, however it is not clear whether both are allowed to be used to denote the same object. Question: If there is no ambiguity, can both the entity and architecture names be used to denote the same object? Proposed Resolution ------------------- Allow either the entity or architecture name to be used as the prefix to denote an object defined in the entity declaration. VASG-ISAC Analysis & Rationale ------------------------------ TBD VASG-ISAC Recommendation for IEEE Std 1076-1987 ----------------------------------------------- TBD VASG-ISAC Recommendation for Future Revisions --------------------------------------------- TBD