VHDL Issue Number:      0225
Classification:         Language Definition Problem
Language Version:       VHDL-87
Summary:                Qualified expressions lead to lexical ambiguity.
Related Issues:         Superseded By IR 1045 (Andy Tsay)
Relevant LRM Sections:
Key Words and Phrases:  Qualified Expressions
Current Status:         Submitted
1076-1993 Disposition:  Superseded (ISAC Issues Outstanding)
Disposition Rationale:  N/A
Superseded By:          1045
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Date Submitted:         1991/03/21
Author of Submission:   Clive Charlwood
Author's Affiliation:   Synopsys Inc.
Author's Post Address:  1098 Alta Ave.
                        Mountain View, CA 94043
Author's Phone Number:  (415) 962-5425
Author's Fax Number:    
Author's Net Address:   crc@synopsys.com
-----------------------
Date Analyzed:          TBD
Author of Analysis:     TBD
Revision Number:        $Revision: 1.10 $
Date Last Revised:      $Date: 1995/08/04 01:45:13 $


Description of Problem
----------------------
(This was Endot VHDL LRM Trouble Report #JM12           8/22/88)

Consider the following VHDL statements:

        X := bit_vector'('1','0');
        B := bit'('1');

Both are intended to be interpreted as qualified expressions.  However, it is
possible that the lexical scanner will tokenize these statements as:

        X   :=   bit_vector   '('   1   ','   0   '   )   ;
        B   :=   bit          '('   1   '     )   ;


Proposed Resolution
-------------------
TBD


VASG-ISAC Analysis & Rationale
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TBD


VASG-ISAC Recommendation for IEEE Std 1076-1987
-----------------------------------------------
TBD


VASG-ISAC Recommendation for Future Revisions
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TBD