VHDL Issue Number:      0226
Classification:         Language Definition Problem
Language Version:       VHDL-87
Summary:                What do default expressions mean in interface
                        variable declarations?
Related Issues:
Relevant LRM Sections:  4.3.3
Key Words and Phrases:  Interface Declarations, Default Expressions
Current Status:         Submitted
1076-1993 Disposition:  Closed (All Issues Completely Addressed)
Disposition Rationale:  Section 4.3.2.1 now defines semantics of interface 
                        object default expression semantics.
Superseded By:          N/A
-----------------------
Date Submitted:         1991/03/21
Author of Submission:   Clive Charlwood
Author's Affiliation:   Synopsys Inc.
Author's Post Address:  1098 Alta Ave.
                        Mountain View, CA 94043
Author's Phone Number:  (415) 962-5425
Author's Fax Number:    
Author's Net Address:   crc@synopsys.com
-----------------------
Date Analyzed:          TBD
Author of Analysis:     TBD
Revision Number:        $Revision: 1.9 $
Date Last Revised:      $Date: 1995/05/13 19:34:42 $


Description of Problem
----------------------
(This was Endot VHDL LRM Trouble Report #JM17           10/5/88)

In the BNF for interface declarations (LRM 4.3.3), the production for
"interface_variable_declaration" contains an optional default expression.
However, it is impossible to use this expression in any way.  Are analyzers
required to permit default expressions to appear in variable interface
elements, and only issue and error message if the corresponding actual is
missing at invocation time?


Proposed Resolution
-------------------
In the Endot tools, we require a mode of IN for any subprogram interface
element which has a default expression.  This effectively forbids the use of
default expressions for class VARIABLE.


VASG-ISAC Analysis & Rationale
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TBD


VASG-ISAC Recommendation for IEEE Std 1076-1987
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TBD


VASG-ISAC Recommendation for Future Revisions
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TBD