VHDL Issue Number: 0227 Classification: Language Definition Problem Language Version: VHDL-87 Summary: Design unit dependencies not (strictly) determined by use clauses. Related Issues: Relevant LRM Sections: 10.4 Key Words and Phrases: Current Status: Submitted 1076-1993 Disposition: Closed (All Issues Completely Addressed) Disposition Rationale: Section 11.4 was revised. Superseded By: N/A ----------------------- Date Submitted: 1991/03/21 Author of Submission: Clive Charlwood Author's Affiliation: Synopsys Inc. Author's Post Address: 1098 Alta Ave. Mountain View, CA 94043 Author's Phone Number: (415) 962-5425 Author's Fax Number: Author's Net Address: crc@synopsys.com ----------------------- Date Analyzed: TBD Author of Analysis: TBD Revision Number: $Revision: 1.9 $ Date Last Revised: $Date: 1995/08/04 01:45:13 $ Description of Problem ---------------------- (This was Endot VHDL LRM Trouble Report #JM15 9/26/88) It is made quite clear in section 10.4 of the LRM, that a use clause "achieves (potential) direct visibility of declarations which are (already) visible by selection." Any VHDL model may be rewritten to eliminate all use clauses and to use selected names starting from a library name. Therefore, it is curious that Section 11.3 states that "dependencies among design units are defined by use clauses." It seems obvious that if a declaration in a package is referenced by selection in an architecture, then the architecture depends on the package even though no use clauses are involved. Proposed Resolution ------------------- In the Endot tools, a dependency exists whenever a reference exists, whether through selected names or use clauses. VASG-ISAC Analysis & Rationale ------------------------------ TBD VASG-ISAC Recommendation for IEEE Std 1076-1987 ----------------------------------------------- TBD VASG-ISAC Recommendation for Future Revisions --------------------------------------------- TBD