VHDL Issue Number: 0228 Classification: Language Definition Problem Language Version: VHDL-87 Summary: May default expressions be utilized in generic map aspects? Related Issues: Relevant LRM Sections: 4.3.3.2, 9.6 Key Words and Phrases: Interface list Current Status: Submitted 1076-1993 Disposition: Closed (All Issues Completely Addressed) Disposition Rationale: Section 9.6 was revised. Superseded By: N/A ----------------------- Date Submitted: 1991/03/21 Author of Submission: Clive Charlwood Author's Affiliation: Synopsys Inc. Author's Post Address: 1098 Alta Ave. Mountain View, CA 94043 Author's Phone Number: (415) 962-5425 Author's Fax Number: Author's Net Address: crc@synopsys.com ----------------------- Date Analyzed: TBD Author of Analysis: TBD Revision Number: $Revision: 1.9 $ Date Last Revised: $Date: 1995/08/04 01:45:13 $ Description of Problem ---------------------- (This was Endot VHDL LRM Trouble Report #JM18 10/5/88) The final paragraph in LRM 4.3.3.2 states, "If an interface element in an interface list includes a default expression for a formal generic ..., then any corresponding association list need not include and association element for that interface element." In this case, the default expression is used. On the other hand, LRM 9.6 states of generic map aspects, "Each local generic ... must be associated exactly once". This appears to be a contradiction. It would be hard to justify a distinction from the general rules on association lists for the special case of generic map aspects. Proposed Resolution ------------------- In the Endot tools, we adopt a loose interpretation of the language in LRM 9.6. We merely require that each local be associated (exactly once) with either an explicit actual or (by default) a default expression. VASG-ISAC Analysis & Rationale ------------------------------ TBD VASG-ISAC Recommendation for IEEE Std 1076-1987 ----------------------------------------------- TBD VASG-ISAC Recommendation for Future Revisions --------------------------------------------- TBD