VHDL Issue Number:      0232
Classification:         Language Definition Problem
Language Version:       VHDL-87
Summary:                Must default expressions in interface declarations
                        be static?
Related Issues:
Relevant LRM Sections:  4.3.3
Key Words and Phrases:  interface declarations, staticness
Current Status:         Submitted
1076-1993 Disposition:  Bugs Fixed, Enhancements Outstanding
Disposition Rationale:  N/A
Superseded By:          N/A
-----------------------
Date Submitted:         1991/03/21
Author of Submission:   Clive Charlwood
Author's Affiliation:   Synopsys Inc.
Author's Post Address:  1098 Alta Ave.
                        Mountain View, CA 94043
Author's Phone Number:  (415) 962-5425
Author's Fax Number:    
Author's Net Address:   crc@synopsys.com
-----------------------
Date Analyzed:          TBD
Author of Analysis:     TBD
Revision Number:        $Revision: 1.9 $
Date Last Revised:      $Date: 1995/05/13 19:34:42 $


Description of Problem
----------------------
(This was VHDL LRM Trouble Report #JM16         10/5/88)

In the BNF for interface declarations (LRM 4.3.3), the italicized word "static"
appears.  However, there is no language in the body of the LRM requiring that
default expressions be static.  For example:

        function F return bit_vector is
                ...
        end F;
        signal S : bit_vector := F;
                ...
        port (P : bit_vector := F);
        process
                variable I : integer;
                procedure Q (J : integer := I) is
                        ...
        begin
                I := 1;
                Q;
                I := 2;
                Q;
        end process;

The signal declaration is definitely legal (The word "static" does not appear
in the BNF for object declarations.)  The port clause is arguably illegal
because the expression "F" is not static.  However, there is no
implementation-related reason for placing stronger restrictions on ports than
on signals.  The expression "I" in the declaration of Q is also not static and
will in fact yield different values when evaluated at different times.


Proposed Resolution
-------------------
In the Endot tools, we have adopted the position that italicized prefixes to
non-terminals in the BNF have the same status as LRM notes.  Therefore, we do
not require static expressions in these contexts.  We only require that the
expression be evaluable at the time the association list is elaborated.  Thus,
for a port default, the default expression may not reference any signals.  For
a subprogram parameter default, we evaluate the expression anew each time the
subprogram is invoked.


VASG-ISAC Analysis & Rationale
------------------------------
TBD


VASG-ISAC Recommendation for IEEE Std 1076-1987
-----------------------------------------------
TBD


VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
TBD