VHDL Issue Number:      0233
Classification:         Language Definition Problem
Language Version:       VHDL-87
Summary:                Unclear definition of "resolved signal."
Related Issues:
Relevant LRM Sections:  4.3.1.2
Key Words and Phrases:
Current Status:         Submitted
1076-1993 Disposition:  Superseded (ISAC Issues Outstanding)
Disposition Rationale:  N/A
Superseded By:          1046
-----------------------
Date Submitted:         1991/03/21
Author of Submission:   Clive Charlwood
Author's Affiliation:   Synopsys Inc.
Author's Post Address:  1098 Alta Ave.
                        Mountain View, CA 94043
Author's Phone Number:  (415) 962-5425
Author's Fax Number:    
Author's Net Address:   crc@synopsys.com
-----------------------
Date Analyzed:          TBD
Author of Analysis:     TBD
Revision Number:        $Revision: 1.9 $
Date Last Revised:      $Date: 1995/08/04 01:45:13 $


Description of Problem
----------------------
(This was Endot VHDL LRM Trouble Report #JM10           7/25/88)

The definition of a resolved signal given at the beginning of Section 4.3.1.2
of the LRM does not seem to include the signal R in the attached example.
Should it? Furthermore, it would seem that R.vect is not a resolved signal, but
that R.rec is.  Finally, what about R.rec.x and R.rec.y?


Proposed Resolution
-------------------
We believe that the term "resolved signal" is applicable only at the level of
granularity at which a resolution function is supplied.  Thus, in the example,
R is not a resolved signal, nor is R.vect.  R.rec is resolved, and so is each
scalar R.vect(n).  However, R.rec.x and R.rec.y are not resolved signals.  Note
that R.rec.y might seem to be resolved, since there is a resolution function
mentioned in its element declaration; however, since this is not the effective
resolution function, we say that it is not a resolved signal, but only a
component of a resolved signal.

        entity E is
          function resfun (A: bit_vector) return bit;
          function wired_or (A:bit_vector) return bit;

          subtype rbit is resfun bit;
          type rbit_vector is array (natural range <>) of rbit;
          type mixed is record
                x : bit;
                y : wired_or bit;
          end record;
          type mixarray is array (integer range <>) of mixed;
         function resmix (A: mixarray) return mixed;
          type big is record
                vect : rbit_vector (7 downto 0);
                rec  : resmix mixed;
          end record;

          signal R : big register;
        end E;


VASG-ISAC Analysis & Rationale
------------------------------
TBD


VASG-ISAC Recommendation for IEEE Std 1076-1987
-----------------------------------------------
TBD


VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
TBD