VHDL Issue Number:      0237
Classification:         Language Definition Problem
Language Version:       VHDL-87
Summary:                When is an enitity bound to the library is references
Related Issues:
Relevant LRM Sections:  11.2
Key Words and Phrases:  Design Libraries
Current Status:         Submitted
1076-1993 Disposition:  Superseded (ISAC Issues Outstanding)
Disposition Rationale:  N/A
Superseded By:          1049
-----------------------
Date Submitted:         1991/03/04
Author of Submission:   Clive Charlwood
Author's Affiliation:   Synopsys Inc.
Author's Post Address:  1098 Alta Ave.
                        Mountain View, CA 94043
Author's Phone Number:  (415) 962-5425
Author's Fax Number:    
Author's Net Address:   crc@synopsys.com
-----------------------
Date Analyzed:          TBD
Author of Analysis:     TBD
Revision Number:        $Revision: 1.9 $
Date Last Revised:      $Date: 1995/08/04 01:45:13 $


Description of Problem
----------------------
The LRM does not define in detail what it means to reference a design unit in a
design library. In particular, it is not clear whether or not the user is free
to "re-map" the mapping between the library logical name and the host
environment after a design unit is placed in the design library.

There are three possible points at which the binding could take place.

1. When the design unit being reference is placed in the
   design library (analyzed).

2. When the entity that is referencing the object is analyzed.

3. When the simulation is elaborated.


Proposed Resolution
-------------------
It is common for people to ship pre-analyzed intermediate files between
groups/companies. Therefore, whatever strategy is adopted should be as flexible
as possible.

The author recommends binding the reference at simulation elaboration time.


VASG-ISAC Analysis & Rationale
------------------------------
TBD


VASG-ISAC Recommendation for IEEE Std 1076-1987
-----------------------------------------------
TBD


VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
TBD