VHDL Issue Number:      0238
Classification:         Language Definition Problem
Language Version:       VHDL-87
Summary:                The grammar is un-necessarily complex.
Related Issues:
Relevant LRM Sections:  1.2, 1.3, 1.3.1
Key Words and Phrases:  simple name
Current Status:         Submitted
1076-1993 Disposition:  Closed (All Issues Completely Addressed)
Disposition Rationale:  LRM is clear now.
Superseded By:          N/A
-----------------------
Date Submitted:         1991/03/04
Author of Submission:   Clive Charlwood
Author's Affiliation:   Synopsys Inc.
Author's Post Address:  1098 Alta Ave.
                        Mountain View, CA 94043
Author's Phone Number:  (415) 962-5425
Author's Fax Number:    
Author's Net Address:   crc@synopsys.com
-----------------------
Date Analyzed:          TBD
Author of Analysis:     TBD
Revision Number:        $Revision: 1.9 $
Date Last Revised:      $Date: 1995/05/13 19:34:42 $


Description of Problem
----------------------
There are several places in the grammar where requiring a simple_name, instead
of a name would simplify the language. In each case, use of something other
than a simple name does not provide any more flexibility.

The three places are:

        Section 1.2:    architecture simple_name of *NAME* is ...
        Section 1.3:    configuration simple_name of *NAME* is ...
        Section 1.3.1:  block_specification  ::=
                         *NAME*
                        |               ...


Proposed Resolution
-------------------
Simplify the grammar as stated.


VASG-ISAC Analysis & Rationale
------------------------------
TBD


VASG-ISAC Recommendation for IEEE Std 1076-1987
-----------------------------------------------
TBD


VASG-ISAC Recommendation for Future Revisions
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TBD