VHDL Issue Number:      0241
Classification:         Language Definition Problem
Language Version:       VHDL-87
Summary:                Certain error requirements are not well-defined.
Related Issues:         0156
Relevant LRM Sections:
Key Words and Phrases:  error detection
Current Status:         Submitted
1076-1993 Disposition:  Superseded (ISAC Issues Outstanding)
Disposition Rationale:  N/A
Superseded By:          1056
-----------------------
Date Submitted:         1991/04/02
Author of Submission:   Chuck Swart
Author's Affiliation:   Mentor Graphics Corporation
Author's Post Address:  8500 S.W. Creekside Place
                        Beaverton, OR 97005-7191
Author's Phone Number:  (503) 626-7000
Author's Fax Number:    
Author's Net Address:   cswart@mentor.com
-----------------------
Date Analyzed:          TBD
Author of Analysis:     TBD
Revision Number:        $Revision: 1.9 $
Date Last Revised:      $Date: 1995/08/04 01:45:13 $


Description of Problem
----------------------
There are a number of problems involving error detection in the language.  Many
of them deal with whether an analyzer/elaborator/simulator must report an
error, may report an error, or must not report an error.

Here are several specific problems:

1.  The LRM uses the term "erroneous" in several places, particularly in
    Chapter 2 and in Chapter 9.  This term is not defined.  It apparently is
    intended to indicate an illegal condition which is not required to be
    detected.

2.  Must an analyzer detect arithmetic errors, such as division by a literal
    zero?  May it detect such errors and report them as errors?  Must it NOT
    report such a condition as an error?

    The LRM states in Chapter 11 that

       "If any error is detected while attempting to analyze a design unit,
        then the attempted analysis is rejected and has no effect whatsoever on
        the current working library."

    so the answer to this question may affect portability.

    Note that in Ada programs with arithmetic errors like this are not allowed
    to be rejected.  Instead, an exception is raised.  The Ada LRM has
    additional requirements which state that no expression which causes an
    exception can be (locally) static, so, for example, "1/0" is not static.
    VHDL does not have exceptions, but does not specify what should be done in
    conditions like this.

3.  What effect do short-circuit operations have on analysis-time error
    detection?  The LRM states:

       "For the short-circuit operations and, or, nand, and nor on types BIT
        and BOOLEAN, the right operand is evaluated only if the value of the
        left operand is not sufficient to determinethe result of the
        operation."

    Does the word "evaluate" here refer only to simulation actions, or does it
    also apply to the analyzer and locally static expressions.  In particular,
    consider the following code fragment:

        IF 1 > 2 AND  (1 / 0) > 1 THEN exec_cnt := exec_cnt + 1; END IF;

    Must an analyzer evaluate 1/0?  May it (and report an error)?  Must it not
    evaluate it?

4.  Can an analyzer reject a design unit which cannot be simulated?  Can a
    design unit which cannot simulate be considered semantically correct?

    Consider the following code fragment:

        P1: process
            begin
              counter <= counter + 1;
            end process P1;

    This process contains no wait statement, nor does it contain a procedure
    which contains a wait statement.  Simulation of a design unit containing
    this process will never finish its initialization phase, since this process
    will never suspend.  Can an analyzer reject a design unit containing this
    process?

A clear answer to this issue becomes more important as the breadth of
applications increases. For example, some vendors claim that this process is
legal and it can be synthesized, even though it cannot be simulated.


Proposed Resolution
-------------------
TBD


VASG-ISAC Analysis & Rationale
------------------------------
TBD


VASG-ISAC Recommendation for IEEE Std 1076-1987
-----------------------------------------------
TBD


VASG-ISAC Recommendation for Future Revisions
---------------------------------------------
TBD